生命周期: | Active | 包装说明: | DIP, |
Reach Compliance Code: | unknown | 风险等级: | 5.59 |
系列: | S | JESD-30 代码: | R-PDIP-T14 |
长度: | 19.305 mm | 逻辑集成电路类型: | J-K FLIP-FLOP |
位数: | 2 | 功能数量: | 2 |
端子数量: | 14 | 最高工作温度: | 70 °C |
最低工作温度: | 输出极性: | COMPLEMENTARY | |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | DIP |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
传播延迟(tpd): | 7 ns | 认证状态: | COMMERCIAL |
座面最大高度: | 5.08 mm | 最大供电电压 (Vsup): | 5.25 V |
最小供电电压 (Vsup): | 4.75 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | NO | 技术: | TTL |
温度等级: | COMMERCIAL | 端子形式: | THROUGH-HOLE |
端子节距: | 2.54 mm | 端子位置: | DUAL |
触发器类型: | NEGATIVE EDGE | 宽度: | 7.62 mm |
最小 fmax: | 80 MHz | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
SN74S113N3 | TI |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,S-TTL,DIP,14PIN,PLASTIC | |
SN74S113NP1 | ROCHESTER |
获取价格 |
J-K Flip-Flop | |
SN74S113NP3 | TI |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,S-TTL,DIP,14PIN,PLASTIC | |
SN74S114 | TI |
获取价格 |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK | |
SN74S114AD | ROCHESTER |
获取价格 |
J-K Flip-Flop, S Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL | |
SN74S114ADR | TI |
获取价格 |
S SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 | |
SN74S114ADR | ROCHESTER |
获取价格 |
暂无描述 | |
SN74S114AN | TI |
获取价格 |
Dual J-K negative-edge-triggered flip-flops with preset, common CLR and CLK 14-PDIP 0 to 7 | |
SN74S114AN | ROCHESTER |
获取价格 |
J-K Flip-Flop, S Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL | |
SN74S114AN3 | ROCHESTER |
获取价格 |
J-K Flip-Flop |