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SN74LVC241APWR PDF预览

SN74LVC241APWR

更新时间: 2024-11-29 15:52:19
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 125K
描述
LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, TSSOP-20

SN74LVC241APWR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56Is Samacsys:N
其他特性:OUTPUT ENABLE ACTIVE HIGH FOR ONE FUNCTION系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G20长度:6.5 mm
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

SN74LVC241APWR 数据手册

 浏览型号SN74LVC241APWR的Datasheet PDF文件第2页浏览型号SN74LVC241APWR的Datasheet PDF文件第3页浏览型号SN74LVC241APWR的Datasheet PDF文件第4页浏览型号SN74LVC241APWR的Datasheet PDF文件第5页浏览型号SN74LVC241APWR的Datasheet PDF文件第6页浏览型号SN74LVC241APWR的Datasheet PDF文件第7页 
SN74LVC241A  
OCTAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
SCAS343E – MARCH 1994 – REVISED JUNE 1998  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
= 3.3 V, T = 25°C  
CC  
A
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
OH  
= 3.3 V, T = 25°C  
CC  
A
Power Off Disables Outputs, Permitting  
Live Insertion  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
13 2A2  
12 1Y4  
11 2A1  
3.3-V V  
)
CC  
GND 10  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
description  
This octal buffer/line driver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVC241A is designed specifically to improve both the performance and density of 3-state  
memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the  
’LVC240A and ’LVC244A, these devices provide the choice of selected combinations of inverting and  
noninverting outputs, symmetrical OE (active-low output-enable) inputs, and complementary OE and  
OE inputs.  
The SN74LVC241A is organized as two 4-bit line drivers with separate output-enable (1OE, 2OE) inputs. When  
1OE is low or 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high or 2OE  
is low, the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is  
determined by the current-sinking or the current-sourcing capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN74LVC241A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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