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SN74LVC161284DGGR PDF预览

SN74LVC161284DGGR

更新时间： 2024-11-20 04:02:07
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德州仪器 - TI /
页数 文件大小 规格书
12页 206K
描述
19-BIT BUS INTERFACE

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SN74LVC161284DGGR 数据手册

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SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005  
DGG OR DL PACKAGE  
(TOP VIEW)  
D
D
D
1.4-kΩ Pullup Resistors Integrated on All  
Open-Drain Outputs Eliminate the Need for  
Discrete Resistors  
HD  
A9  
1
48 DIR  
47 Y9  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2
A10  
A11  
A12  
A13  
3
46 Y10  
45 Y11  
4
Designed for the IEEE Std 1284-I (Level 1  
Type) and IEEE Std 1284-II (Level 2 Type)  
Electrical Specifications  
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44  
Y12  
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43 Y13  
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25  
V
V
CABLE  
CC  
CC  
A1  
D
D
Flow-Through Architecture Optimizes PCB  
Layout  
8
B1  
B2  
GND  
B3  
B4  
B5  
B6  
GND  
B7  
B8  
9
A2  
GND  
A3  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin-Shrink  
Small-Outline (DGG) Packages  
10  
11  
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24  
A4  
A5  
A6  
description/ordering information  
GND  
A7  
The SN74LVC161284 is designed for 3-V to 3.6-V  
V
operation.  
This  
device  
provides  
CC  
A8  
asynchronous two-way communication between  
data buses. The control-function implementation  
minimizes external timing requirements.  
V
V
CABLE  
CC  
CC  
PERI LOGIC IN  
PERI LOGIC OUT  
C14  
C15  
C16  
A14  
A15  
A16  
A17  
This device has eight bidirectional bits; data can  
flow in the A-to-B direction when DIR is high and  
in the B-to-A direction when DIR is low. This  
device also has five drivers, which drive the cable  
side, and four receivers. The SN74LVC161284  
has one receiver dedicated to the HOST LOGIC  
line and a driver to drive the PERI LOGIC line.  
C17  
HOST LOGIC OUT  
HOST LOGIC IN  
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in  
a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive  
requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel  
peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have  
a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low  
state or if the output voltage is above V  
CABLE. If V  
CABLE is off, PERI LOGIC OUT is set to low.  
CC  
CC  
The device has two supply voltages. V  
is designed for 3-V to 3.6-V operation. V  
CABLE supplies the inputs  
CC  
CC  
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even  
when V CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.  
CC  
The SN74LVC161284 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2005 Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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SN74LVC161284DGGR 替代型号

型号 品牌 替代类型 描述 数据表
74LVC161284DGGRG4 TI

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 19-BIT BUS INTERFACE
SN74LVCE161284DGGR TI

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 19 BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERROR FREE POWER UP
SN74LVCZ161284AGR TI

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 19-BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

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