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SN74LVC02AQDRQ1 PDF预览

SN74LVC02AQDRQ1

更新时间: 2024-11-05 11:06:19
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 236K
描述
汽车类 4 通道、2 输入、2V 至 3.6V 或非门 | D | 14 | -40 to 125

SN74LVC02AQDRQ1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:8 weeks风险等级:5.16
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.024 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):0.01 mA
Prop。Delay @ Nom-Sup:5.5 ns传播延迟(tpd):6.5 ns
认证状态:Not Qualified施密特触发器:NO
筛选级别:AEC-Q100座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.91 mmBase Number Matches:1

SN74LVC02AQDRQ1 数据手册

 浏览型号SN74LVC02AQDRQ1的Datasheet PDF文件第2页浏览型号SN74LVC02AQDRQ1的Datasheet PDF文件第3页浏览型号SN74LVC02AQDRQ1的Datasheet PDF文件第4页浏览型号SN74LVC02AQDRQ1的Datasheet PDF文件第5页浏览型号SN74LVC02AQDRQ1的Datasheet PDF文件第6页浏览型号SN74LVC02AQDRQ1的Datasheet PDF文件第7页 
SN74LVC02A-Q1  
www.ti.com............................................................................................................................................................. SCES465CJULY 2003REVISED APRIL 2008  
QUADRUPLE 2-INPUT POSITIVE-NOR GATE  
1
FEATURES  
D OR PW PACKAGE  
Qualified for Automotive Applications  
(TOP VIEW)  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1Y  
1A  
1
2
3
4
5
6
7
14 VCC  
13  
12  
11  
10  
9
4Y  
4B  
4A  
3Y  
3B  
3A  
1B  
Inputs Accept Voltages to 5.5 V  
2Y  
2A  
2B  
8
GND  
DESCRIPTION/ORDERING INFORMATION  
The quadruple 2-input positive-NOR gate is designed for 2.7-V to 3.6-V VCC operation.  
The SN74LVC02A-Q1 performs the Boolean function Y = A + B or Y = A • B in positive logic.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
Tape and reel  
Tape and reel  
ORDERABLE PART NUMBER  
SN74LVC02AQDRQ1  
TOP-SIDE MARKING  
LVC02AQ  
LC02AQ  
SOIC – D  
–40°C to 125°C  
TSSOP – PW  
SN74LVC02AQPWRQ1  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
FUNCTION TABLE  
(EACH GATE)  
INPUTS  
OUTPUT  
Y
A
H
X
L
B
X
H
L
L
L
H
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)  
A
Y
B
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2008, Texas Instruments Incorporated  

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