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SN74LV374PWLE

更新时间： 2024-11-15 02:58:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
11页 251K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74LV374PWLE 数据手册

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SCLS197B − FEBRUARY 1993 − REVISED APRIL 1996  
SN54LV374 . . . J OR W PACKAGE  
SN74LV374 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
> 2 V at V , T = 25°C  
CC  
A
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
D
D
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
GND 10  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
SN54LV374 . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
These octal edge-triggered D-type flip-flops are  
designed for 2.7-V to 5.5-V V operation.  
17  
16  
CC  
15 6Q  
14  
9 10 11 12 13  
The ’LV374 feature 3-state outputs designed  
specifically for driving highly capacitive or  
relatively low-impedance loads. These devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
6D  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data  
(D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either as normal logic state (high  
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines  
without need for interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
The SN74LV374 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV374 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74LV374 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...11

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