5秒后页面跳转
SN74LS75N PDF预览

SN74LS75N

更新时间: 2024-11-24 23:03:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 103K
描述
4-BIT D LATCH

SN74LS75N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:8.61
系列:LSJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
负载电容(CL):15 pF逻辑集成电路类型:D LATCH
位数:2功能数量:2
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):12 mA
传播延迟(tpd):25 ns认证状态:Not Qualified
座面最大高度:4.44 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:HIGH LEVEL宽度:7.62 mm
Base Number Matches:1

SN74LS75N 数据手册

 浏览型号SN74LS75N的Datasheet PDF文件第2页浏览型号SN74LS75N的Datasheet PDF文件第3页浏览型号SN74LS75N的Datasheet PDF文件第4页 
SN54/74LS75  
SN54/74LS77  
4-BIT D LATCH  
The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-  
porary storage for binary information between processing units and input/out-  
put or indicator units. Information present at a data (D) input is transferred to  
the Q output when the Enable is HIGH and the Q output will follow the data  
input as long as the Enable remains HIGH. When the Enable goes LOW, the  
information (that was present at the data input at the time the transition oc-  
curred) is retained at the Q output until the Enable is permitted to go HIGH.  
The SN54/74LS75 features complementary Q and Q output from a 4-bit  
latch and is available in the 16-pin packages. For higher component density  
applications the SN54/74LS77 4-bit latch is available in the 14-pin package  
with Q outputs omitted.  
4-BIT D LATCH  
LOW POWER SCHOTTKY  
CONNECTION DIAGRAMS DIP (TOP VIEW)  
J SUFFIX  
CERAMIC  
CASE 620-09  
Q
Q
Q
E
GND  
12  
Q
Q
Q
3
0
1
1
0–1  
13  
2
2
16  
15  
14  
11  
10  
9
16  
16  
1
SN54/74LS75  
N SUFFIX  
PLASTIC  
CASE 648-08  
1
2
3
4
5
6
8
7
1
Q
D
D
E
V
D
D
Q
3
0
0
1
2–3  
CC  
2
3
Q
Q
E
GND  
11  
NC  
10  
Q
Q
3
0
1
0–1  
12  
2
D SUFFIX  
SOIC  
CASE 751B-03  
14  
13  
9
8
16  
1
SN54/74LS77  
J SUFFIX  
CERAMIC  
CASE 632-08  
1
2
3
4
5
6
7
NC  
14  
D
D
E
V
D
D
3
0
1
2–3  
CC  
2
1
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
N SUFFIX  
PLASTIC  
CASE 646-06  
D –D  
Data Inputs  
0.5 U.L.  
2.0 U.L.  
2.0 U.L.  
10 U.L.  
10 U.L.  
0.25 U.L.  
1.0 U.L.  
1.0 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
1
4
E
E
Q –Q  
Enable Input Latches 0, 1  
Enable Input Latches 2, 3  
Latch Outputs (Note b)  
0–1  
2–3  
1
14  
1
4
4
Q –Q  
Complimentary Latch Outputs (Note b)  
1
NOTES:  
a) 1 Unit Load (U.L.) = 40 µA HIGH.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
Temperature Ranges.  
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
TRUTH TABLE  
(Each latch)  
ORDERING INFORMATION  
NOTES:  
= bit time before enable  
t
t
n+1  
n
SN54LSXXJ  
SN74LSXXN  
SN74LSXXD  
Ceramic  
Plastic  
SOIC  
t
n
negative-going transition  
= bit time after enable  
D
H
L
Q
H
L
t
n+1  
negative-going transition  
FAST AND LS TTL DATA  
5-75  

SN74LS75N 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS75N TI

功能相似

4-BIT BISTABLE LATCHES

与SN74LS75N相关器件

型号 品牌 获取价格 描述 数据表
SN74LS75N1 TI

获取价格

IC,LATCH,SINGLE,4-BIT,LS-TTL,DIP,16PIN,PLASTIC
SN74LS75N-10 TI

获取价格

LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-1
SN74LS75NDS MOTOROLA

获取价格

LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-1
SN74LS75NE4 TI

获取价格

Quad bistable latches 16-PDIP 0 to 70
SN74LS75NP1 TI

获取价格

IC,LATCH,SINGLE,4-BIT,LS-TTL,DIP,16PIN,PLASTIC
SN74LS75NP3 TI

获取价格

IC,LATCH,SINGLE,4-BIT,LS-TTL,DIP,16PIN,PLASTIC
SN74LS75NSR TI

获取价格

4-BIT BISTABLE LATCHES
SN74LS76 ONSEMI

获取价格

LOW POWER SCHOTTKY
SN74LS76 TI

获取价格

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR
SN74LS76 MOTOROLA

获取价格

DUAL JK FLIP-FLOP WITH SET AND CLEAR