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SN74LS641 PDF预览

SN74LS641

更新时间: 2024-11-20 23:06:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线收发器
页数 文件大小 规格书
3页 88K
描述
OCTAL BUS TRANSCEIVERS

SN74LS641 数据手册

 浏览型号SN74LS641的Datasheet PDF文件第2页浏览型号SN74LS641的Datasheet PDF文件第3页 
SN54/74LS640  
SN54/74LS641  
SN54/74LS642  
SN54/74LS645  
OCTAL BUS TRANSCEIVERS  
These octal bus transceivers are designed for asynchronous two-way  
communication between data buses. Control function implementation  
minimizes external timing requirements. These circuits allow data transmis-  
sion from the A bus to B or from the B bus to A bus depending upon the logic  
level of the direction control (DIR) input. Enable input (G) can disable the  
device so that the buses are effectively isolated.  
OCTAL BUS TRANSCEIVERS  
LOW POWER SCHOTTKY  
DEVICE  
LS640  
LS641  
LS642  
LS645  
OUTPUT  
3-State  
Open-Collector  
Open-Collector  
3-State  
LOGIC  
Inverting  
True  
Inverting  
True  
J SUFFIX  
CERAMIC  
CASE 732-03  
FUNCTION TABLE  
20  
CONTROL  
INPUTS  
OPERATION  
1
LS640  
LS642  
LS641  
LS645  
G
L
DIR  
L
N SUFFIX  
PLASTIC  
CASE 738-03  
B data to A bus  
A data to B bus  
Isolation  
B data to A bus  
A data to B bus  
Isolation  
20  
L
H
1
H
X
H = HIGH Level, L = LOW Level, X = Irrelevant  
DW SUFFIX  
SOIC  
CASE 751D-03  
20  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
CONNECTION DIAGRAMS DIP (TOP VIEW)  
ENABLE  
ENABLE  
V
B1  
18  
B2  
17  
B3  
16  
B4  
15  
B5  
14  
B6 B7  
B8  
11  
V
B1  
18  
B2  
17  
B3  
16  
B4  
15  
B5  
14  
B6 B7  
B8  
11  
G
G
CC  
20  
CC  
20  
19  
13  
12  
19  
13  
12  
1
2
3
4
5
6
8
9
10  
1
2
3
4
5
6
8
9
10  
7
7
DIR A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8 GND  
DIR A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8 GND  
SN54/74LS640  
SN54/74LS642  
SN54/74LS641  
SN54/74LS645  
FAST AND LS TTL DATA  
5-1  

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