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SN74LS569DW PDF预览

SN74LS569DW

更新时间： 2024-11-28 23:03:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 262K
描述
FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS

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中文翻译

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SN74LS569DW 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
Is Samacsys：N计数方向：BIDIRECTIONAL
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：25000000 Hz工作模式：SYNCHRONOUS
功能数量：1端子数量：20
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
电源：5 V认证状态：Not Qualified
子类别：Counters标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

SN74LS569DW 数据手册

 浏览型号SN74LS569DW的Datasheet PDF文件第2页浏览型号SN74LS569DW的Datasheet PDF文件第3页浏览型号SN74LS569DW的Datasheet PDF文件第4页浏览型号SN74LS569DW的Datasheet PDF文件第5页浏览型号SN74LS569DW的Datasheet PDF文件第6页浏览型号SN74LS569DW的Datasheet PDF文件第7页 
SN54/74LS569A  
FOUR-BIT UP/DOWN COUNTER  
WITH THREE-STATE OUTPUTS  
The SN54/74LS569A is designed as programmable up/down BCD and  
Binary counters respectively. These devices have 3-state outputs for use in  
bus organized systems. With the exception of output enable (OE) and  
asynchronous clear (ACLR), all functions occur on the positive edge of the  
clock pulse (CP).  
FOUR-BIT UP/DOWN COUNTER  
WITH THREE-STATE OUTPUTS  
LOW POWER SCHOTTKY  
When the LOAD input is LOW, the outputs will be programmed by the  
parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the  
counters occurs only when CEP and CET are LOW and LOAD is HIGH.  
Direction of the count is controlled by the up-down input (U/D), HIGH counts  
up and LOW counts down. High-speed counting and cascading is implement-  
ed by internal look-ahead carry logic and an active LOW ripple carry output  
(RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and  
during down-count it is also LOW at binary 0. During normal cascading  
operation RCO connected to the succeeding block at CET is the only  
requisite. When counting and when RCO is LOW, the clocked carry output  
(CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW  
time of the clock pulse. Two active LOW reset lines are provided, a master  
reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in  
a HIGH state, the output control (OE) input forces the counter output into a  
HIGH impedance state and when LOW, the counter outputs are enabled.  
J SUFFIX  
CERAMIC  
CASE 732-03  
20  
1
N SUFFIX  
PLASTIC  
CASE 738-03  
20  
1
• ESD > 3500 Volts  
DW SUFFIX  
SOIC  
CASE 751D-03  
CONNECTION DIAGRAM (TOP VIEW)  
20  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
Note: Pin 1 is marked  
for orientation.  
GUARANTEED OPERATING RANGES  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
V
CC  
Supply Voltage  
54  
74  
4.5  
4.75  
5.0  
5.0  
5.5  
5.25  
V
T
Operating Ambient Temperature Range  
Output Current — High Except RCO, CCO  
54  
74  
–55  
0
25  
25  
125  
70  
°C  
A
I
54  
74  
–1.0  
–2.6  
mA  
OH  
I
I
Output Current — High RCO, CCO  
54, 74  
–0.44  
mA  
mA  
OH  
Output Current — Low Except RCO, CCO  
54  
74  
12  
24  
OL  
I
Output Current — Low, RCO, CCO  
54  
74  
4.0  
8.0  
mA  
OL  
FAST AND LS TTL DATA  
5-573  
12345678

中文翻译

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