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SN74LS48JDS PDF预览

SN74LS48JDS

更新时间: 2024-11-29 13:02:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器
页数 文件大小 规格书
3页 104K
描述
LS SERIES, SEVEN SEGMENT DECODER/DRIVER, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16

SN74LS48JDS 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.63
Is Samacsys:N系列:LS
输入调节:STANDARDJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.495 mm
逻辑集成电路类型:SEVEN SEGMENT DECODER/DRIVER功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出特性:OPEN-COLLECTOR WITH PULLUP
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):100 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN74LS48JDS 数据手册

 浏览型号SN74LS48JDS的Datasheet PDF文件第2页浏览型号SN74LS48JDS的Datasheet PDF文件第3页 
SN54/74LS48  
BCD TO 7-SEGMENT  
DECODER  
The SN54/74LS48 is a BCD to 7-Segment Decoder consisting of NAND  
gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates  
and one driver are connected in pairs to make BCD data and its complement  
available to the seven decoding AND-OR-INVERT gates. The remaining  
NAND gate and three input buffers provide lamp test, blanking input/ripple-  
blanking input for the LS48.  
BCD TO 7-SEGMENT  
DECODER  
LOW POWER SCHOTTKY  
The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on  
the state of the auxiliary inputs, decodes this data to drive other components.  
The relative positive logic output levels, as well as conditions required at the  
auxiliary inputs, are shown in the truth tables.  
The LS48 circuit incorporates automatic leading and/or trailing edge  
zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated any  
time when the BI/RBO node is HIGH. Both devices contain an overriding  
blanking input (BI) which can be used to control the lamp intensity by varying  
the frequency and duty cycle of the BI input signal or to inhibit the outputs.  
Lamp Intensity Modulation Capability (BI/RBO)  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
Internal Pull-Ups Eliminate Need for External Resistors  
Input Clamp Diodes Eliminate High-Speed Termination Effects  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
CONNECTION DIAGRAM DIP (TOP VIEW)  
1
V
f
g
a
b
c
d
e
CC  
16  
15  
14  
13  
12  
11  
10  
9
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
1
2
3
4
5
6
8
7
B
C
LT BI/RBO RBI  
D
A
GND  
SN54LSXXJ  
SN74LSXXN  
SN74LSXXD  
Ceramic  
Plastic  
SOIC  
LOGIC DIAGRAM  
a
b
LOGIC SYMBOL  
A
7
1
2
6
3
5
B
INPUT  
A
B
C
D
LT RBI  
C
D
c
d
e
SN54/74LS48  
OUTPUT  
BI/  
g
RBO  
a
b
c
d
e
f
BLANKING INPUT OR  
RIPPLE-BLANKING  
OUTPUT  
13 12 11 10  
9
15 14  
4
V
= PIN 16  
CC  
GND = PIN 8  
f
RIPPLE-BLANKING  
INPUT  
LAMP-TEST  
INPUT  
g
FAST AND LS TTL DATA  
5-59  

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