5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 移位寄存器> SN74LS165ADG4
SN74LS165ADG4 PDF预览

SN74LS165ADG4

更新时间： 2024-11-27 05:17:19
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
15页 342K
描述
PARALLEL-LOAD-8-BIT SHIFT REGISTERS

阅读下载

中文翻译

获取价格

SN74LS165ADG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.26
Is Samacsys：N其他特性：SISO OPERATION ALSO AVAILABLE
计数方向：RIGHT系列：LS
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm逻辑集成电路类型：PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup：25000000 Hz湿度敏感等级：1
位数：8功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5 V传播延迟（tpd）：25 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Shift Registers最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：25 MHzBase Number Matches：1

SN74LS165ADG4 数据手册

 浏览型号SN74LS165ADG4的Datasheet PDF文件第2页浏览型号SN74LS165ADG4的Datasheet PDF文件第3页浏览型号SN74LS165ADG4的Datasheet PDF文件第4页浏览型号SN74LS165ADG4的Datasheet PDF文件第5页浏览型号SN74LS165ADG4的Datasheet PDF文件第6页浏览型号SN74LS165ADG4的Datasheet PDF文件第7页 
SN54165, SN54LS165A, SN74165, SN74LS165A  
PARALLEL-LOAD 8-BIT SHIFT REGISTERS  
The SN54165 and SN74165 devices  
are obsolete and are no longer supplied.  
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002  
SN54165, SN54LS165A . . . J OR W PACKAGE  
SN74165 . . . N PACKAGE  
Complementary Outputs  
Direct Overriding Load (Data) Inputs  
Gated Clock Inputs  
SN74LS165A . . . D, N, OR NS PACKAGE  
(TOP VIEW)  
Parallel-to-Serial Data Conversion  
SH/LD  
CLK  
E
V
CC  
CLK INH  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
TYPICAL MAXIMUM  
CLOCK FREQUENCY POWER DISSIPATION  
TYPICAL  
TYPE  
’165  
D
C
B
A
26 MHz  
35 MHz  
210 mW  
90 mW  
F
G
H
’LS165A  
description  
Q
SER  
H
GND  
Q
H
The ’165 and ’LS165A are 8-bit serial shift  
registers that shift the data in the direction of Q  
A
toward Q when clocked. Parallel-in access to  
H
SN54LS165A . . . FK PACKAGE  
(TOP VIEW)  
each stage is made available by eight individual,  
direct data inputs that are enabled by a low level  
at the shift/load (SH/LD) input. These registers  
also feature gated clock (CLK) inputs and  
complementary outputs from the eighth bit. All  
inputs  
are  
diode-clamped  
to minimize  
3
2
1
20 19  
18  
transmission-line effects, thereby simplifying  
system design.  
4
5
6
7
8
D
C
NC  
B
A
E
F
NC  
G
17  
16  
15  
14  
Clocking is accomplished through a two-input  
positive-NOR gate, permitting one input to be  
used as a clock-inhibit function. Holding either of  
the clock inputs high inhibits clocking, and holding  
either clock input low with SH/LD high enables the  
other clock input. Clock inhibit (CLK INH) should  
be changed to the high level only while CLK is  
high. Parallel loading is inhibited as long asSH/LD  
is high. Data at the parallel inputs are loaded  
directly into the register while SH/LD is low,  
independently of the levels of CLK, CLK INH, or  
serial (SER) inputs.  
H
9 10 11 12 13  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

下载PDF

SN74LS165ADG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS165ADRG4 TI

完全替代

 PARALLEL-LOAD-8-BIT SHIFT REGISTERS
SN74LS165ADRE4 TI

完全替代

 PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LS165ADE4 TI

完全替代

 PARALLEL-LOAD 8-BIT SHIFT REGISTERS

与SN74LS165ADG4相关器件

型号 品牌 获取价格 描述 数据表
SN74LS165ADR TI

获取价格

 		PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LS165ADRE4 TI

获取价格

 		PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LS165ADRG4 TI

获取价格

 		PARALLEL-LOAD-8-BIT SHIFT REGISTERS
SN74LS165AJ TI

获取价格

 		PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LS165AJ4 TI

获取价格

 		IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,CERAMIC
SN74LS165AJP4 TI

获取价格

 		IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,CERAMIC
SN74LS165AN TI

获取价格

 		PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LS165AN3 TI

获取价格

 		PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LS165ANE4 TI

获取价格

 		PARALLEL-LOAD-8-BIT SHIFT REGISTERS
SN74LS165ANP1 TI

获取价格

 		IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,PLASTIC

与SN74LS165ADG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证