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SN74LS160AJD PDF预览

SN74LS160AJD

更新时间： 2024-11-24 13:13:51
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摩托罗拉 - MOTOROLA 计数器
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SN74LS160AJD 数据手册

 浏览型号SN74LS160AJD的Datasheet PDF文件第2页浏览型号SN74LS160AJD的Datasheet PDF文件第3页浏览型号SN74LS160AJD的Datasheet PDF文件第4页浏览型号SN74LS160AJD的Datasheet PDF文件第5页浏览型号SN74LS160AJD的Datasheet PDF文件第6页 
SN54/74LS160A  
SN54/74LS161A  
SN54/74LS162A  
SN54/74LS163A  
BCD DECADE COUNTERS/  
4-BIT BINARY COUNTERS  
The LS160A/161A/162A/163A are high-speed 4-bit synchronous count-  
ers. They are edge-triggered, synchronously presettable, and cascadable  
MSI building blocks for counting, memory addressing, frequency division and  
other applications. The LS160A and LS162A count modulo 10 (BCD). The  
LS161A and LS163A count modulo 16 (binary.)  
BCD DECADE COUNTERS/  
4-BIT BINARY COUNTERS  
The LS160A and LS161A have an asynchronous Master Reset (Clear)  
input that overrides, and is independent of, the clock and all other control  
inputs. TheLS162AandLS163AhaveaSynchronousReset(Clear)inputthat  
overrides all other control inputs, but is active only during the rising clock  
edge.  
LOW POWER SCHOTTKY  
BCD (Modulo 10)  
LS160A  
Binary (Modulo 16)  
LS161A  
J SUFFIX  
CERAMIC  
CASE 620-09  
Asynchronous Reset  
Synchronous Reset  
LS162A  
LS163A  
16  
1
• Synchronous Counting and Loading  
• Two Count Enable Inputs for High Speed Synchronous Expansion  
• Terminal Count Fully Decoded  
• Edge-Triggered Operation  
• Typical Count Rate of 35 MHz  
• ESD > 3500 Volts  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
V
TC  
15  
Q
Q
Q
Q
3
CET  
10  
PE  
9
CC  
0
1
2
D SUFFIX  
16  
14  
13  
12  
11  
SOIC  
CASE 751B-03  
NOTE:  
16  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
1
ORDERING INFORMATION  
*MR for LS160A and LS161A  
*SR for LS162A and LS163A  
SN54LSXXXJ Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
1
2
3
4
5
6
8
7
*R  
CP  
P
P
P
P
3
CEP GND  
0
1
2
PIN NAMES  
LOADING (Note a)  
LOGIC SYMBOL  
HIGH  
LOW  
9
3
4
5
6
PE  
Parallel Enable (Active LOW) Input  
Parallel Inputs  
Count Enable Parallel Input  
Count Enable Trickle Input  
Clock (Active HIGH Going Edge) Input  
Master Reset (Active LOW) Input  
Synchronous Reset (Active LOW) Input  
Parallel Outputs (Note b)  
1.0 U.L.  
0.5 U.L.  
0.5 U.L.  
1.0 U.L.  
0.5 U.L.  
0.5 U.L.  
1.0 U.L.  
10 U.L.  
10 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.5 U.L.  
P –P  
0
3
PE  
CEP  
P
P
P
P
CEP  
CET  
CP  
0
1
2
3
7
TC  
15  
CET  
CP  
10  
2
MR  
SR  
*R  
Q
Q
Q
Q
2 3  
0
1
Q –Q  
5 (2.5) U.L.  
5 (2.5) U.L.  
0
3
TC  
Terminal Count Output (Note b)  
1
14 13 12 11  
= PIN 16  
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
Temperature Ranges.  
V
CC  
GND = PIN 8  
*MR for LS160A and LS161A  
*SR for LS162A and LS163A  
FAST AND LS TTL DATA  
5-1  
123456

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