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SN74LS113D PDF预览

SN74LS113D

更新时间: 2024-11-17 23:06:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
4页 143K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN74LS113D 数据手册

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SN54/74LS113A  
DUAL JK NEGATIVE  
EDGE-TRIGGERED FLIP-FLOP  
The SN54/74LS113A offers individual J, K, set, and clock inputs. These  
monolithic dual flip-flops are designed so that when the clock goes HIGH, the  
inputs are enabled and data will be accepted. The logic level of the J and K  
inputs may be allowed to change when the clock pulse is HIGH and the  
bistable will perform according to the truth table as long as minimum setup  
times are observed. Input data is transferred to the outputs on the  
negative-going edge of the clock pulse.  
DUAL JK NEGATIVE  
EDGE-TRIGGERED FLIP-FLOP  
LOW POWER SCHOTTKY  
LOGIC DIAGRAM (Each Flip-Flop)  
J SUFFIX  
CERAMIC  
CASE 632-08  
14  
1
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
1
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
ORDERING INFORMATION  
SN54LSXXXJ Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
MODE SELECT — TRUTH TABLE  
INPUTS  
J
OUTPUTS  
OPERATING MODE  
S
D
K
Q
Q
Set  
Toggle  
Load “0” (Reset)  
Load “1” (Set)  
Hold  
L
X
h
l
h
l
X
h
h
l
H
q
L
H
q
L
q
H
L
q
H
H
H
H
LOGIC SYMBOL  
l
H, h = HIGH Voltage Level  
L, I = LOW Voltage Level  
X = Don’t Care  
l, h (q) = Lower case letters indicate the state of the referenced input (or output)  
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.  
FAST AND LS TTL DATA  
5-189  

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