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SN74LS109D PDF预览

SN74LS109D

更新时间: 2024-11-05 23:03:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
4页 150K
描述
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

SN74LS109D 数据手册

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SN54/74LS109A  
DUAL JK POSITIVE  
EDGE-TRIGGERED FLIP-FLOP  
The SN54/74LS109A consists of two high speed completely independent  
transition clocked JK flip-flops. The clocking operation is independent of rise  
and fall times of the clock waveform. The JK design allows operation as a D  
flip-flop by simply connecting the J and K pins together.  
DUAL JK POSITIVE  
EDGE-TRIGGERED FLIP-FLOP  
LOW POWER SCHOTTKY  
LOGIC DIAGRAM  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
MODE SELECT — TRUTH TABLE  
INPUTS  
OUTPUTS  
OPERATING MODE  
ORDERING INFORMATION  
S
D
C
J
K
Q
Q
D
SN54LSXXXJ Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
Set  
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
X
X
X
h
h
l
H
L
H
H
q
L
H
H
L
q
q
Reset (Clear)  
*Undetermined  
Load “1” (Set)  
Hold  
Toggle  
Load “0” (Reset)  
h
l
q
L
LOGIC SYMBOL  
l
H
* BothoutputswillbeHIGHwhilebothS andC areLOW,buttheoutputstates  
D
D
are unpredictable if S and C go HIGH simultaneously.  
D
H, h = HIGH Voltage Level  
L, I = LOW Voltage Level  
X = Don’t Care  
D
l, h (q) = Lower case letters indicate the state of the referenced input (or output)  
l, h (q) = one set-up time prior to the LOW to HIGH clock transition.  
FAST AND LS TTL DATA  
5-181  

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