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SN74HCT74NSRE4

更新时间： 2024-11-23 05:17:23
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
15页 533K
描述
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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中文翻译

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SN74HCT74NSRE4 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ ꢀꢁꢇ ꢃꢄ ꢅꢆ ꢇꢃ  
ꢉꢊꢋ ꢌ ꢉꢍꢆ ꢎꢏ ꢐ ꢏꢑ ꢀꢒ ꢆ ꢒꢓꢐ ꢍꢐꢉꢔ ꢐꢍꢆ ꢕꢒ ꢔ ꢔꢐ ꢕꢐꢉ ꢖ ꢌꢒ ꢏ ꢍꢖ ꢌꢑ ꢏꢀ  
ꢗ ꢒꢆ ꢄ ꢅꢌ ꢐꢋꢕ ꢋꢁꢉ ꢏ ꢕꢐ ꢀ ꢐꢆ  
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004  
SN54HCT74 . . . J OR W PACKAGE  
SN74HCT74 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 40-µA Max I  
CC  
1
2
3
4
5
6
7
1CLR  
1D  
V
CC  
13 2CLR  
14  
Typical t = 17 ns  
pd  
4-mA Output Drive at 5 V  
12  
11  
10  
9
1CLK  
1PRE  
1Q  
2D  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
2CLK  
2PRE  
2Q  
1Q  
description/ordering information  
8
GND  
2Q  
The ’HCT74 devices contain two independent  
D-type positive-edge-triggered flip-flops. A low  
level at the preset (PRE) or clear (CLR) inputs sets  
or resets the outputs, regardless of the levels of  
the other inputs. When PRE and CLR are inactive  
(high), data at the data (D) input meeting the setup  
time requirements are transferred to the outputs  
on the positive-going edge of the clock (CLK)  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the rise time of CLK.  
Following the hold-time interval, data at the  
D input may be changed without affecting the  
levels at the outputs.  
SN54HCT74 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
2CLK  
1PRE  
NC  
15 NC  
14  
9 10 11 12 13  
2PRE  
1Q  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HCT74N  
SN74HCT74N  
SN74HCT74D  
SN74HCT74DR  
SN74HCT74DT  
SN74HCT74NSR  
SN74HCT74DBR  
SN74HCT74PW  
SN74HCT74PWR  
SN74HCT74PWT  
SNJ54HCT74J  
HCT74  
SOP − NS  
HCT74  
HT74  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HT74  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HCT74J  
SNJ54HCT74W  
SNJ54HCT74FK  
−55°C to 125°C  
SNJ54HCT74W  
SNJ54HCT74FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢊ ꢁ ꢌꢐꢀꢀ ꢑ ꢆꢄ ꢐꢕꢗ ꢒꢀ ꢐ ꢁ ꢑꢆꢐꢉ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢏꢕ ꢑ ꢉ ꢊ ꢅꢆ ꢒꢑ ꢁ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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SN74HCT74NSRE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74HCT74PWR TI

完全替代

 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HCT74NSR TI

完全替代

 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HCT74PW TI

完全替代

 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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 		DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HCT74PWE4 TI

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 		DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
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 		Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 85
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SN74HCT74PWRE4 TI

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 		DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HCT74PWRG4 TI

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 		HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN,
SN74HCT74PWT TI

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 		DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HCT74PWTE4 TI

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