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SN74HCT623DWR-00 PDF预览

SN74HCT623DWR-00

更新时间: 2024-11-26 15:52:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
10页 288K
描述
HCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20

SN74HCT623DWR-00 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列:HCTJESD-30 代码:R-PDSO-G20
长度:12.8 mm负载电容(CL):150 pF
逻辑集成电路类型:BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):47 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

SN74HCT623DWR-00 数据手册

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SN54HCT623, SN74HCT623  
OCTAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCLS016C – MARCH 1984 – REVISED MARCH 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
Low Power Consumption, 80-µA Max I  
Inputs Are TTL-Voltage Compatible  
Lock Bus-Latch Capability  
True Logic  
CC  
Typical t = 11 ns  
pd  
±6-mA Output Drive at 5 V  
High-Current 3-State Outputs Can Drive Up  
To 15 LSTTL Loads  
Low Input Current of 1 µA Max  
SN54HCT623 . . . J OR W PACKAGE  
SN74HCT623 . . . DW OR N PACKAGE  
(TOP VIEW)  
SN54HCT623 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OEAB  
A1  
V
CC  
OEBA  
3
2
1
20 19  
18  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B1  
B2  
B3  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15 B4  
14  
9 10 11 12 13  
B5  
description/ordering information  
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The  
control-function implementation allows for maximum flexibility in timing.  
The ’HCT623 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus,  
depending upon the logic levels at the output-enable (OEAB and OEBA) inputs.  
The output-enable inputs disable the device so that the buses are effectively isolated. The dual-enable  
configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and OEBA.  
Each output reinforces its input in this transceiver configuration. When both OEAB and OEBA are enabled and  
all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total)  
remain at their last states. The 8-bit codes appearing on the two sets of buses are identical.  
To ensure the high-impedance state during power up or power down, OEBA should be tied to V  
through a  
CC  
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor  
is determined by the current-sinking/current-sourcing capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
SOIC – DW  
CDIP – J  
Tube  
Tube  
Tube  
Tube  
Tube  
SN74HCT623N  
SN74HCT623DW  
SNJ54HCT623J  
SNJ54HCT623W  
SNJ54HCT623FK  
SN74HCT623N  
HCT623  
–40°C to 85°C  
–55°C to 125°C  
SNJ54HCT623J  
SNJ54HCT623W  
SNJ54HCT623FK  
CFP – W  
LCCC – FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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