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SN74HCT00PWE4 PDF预览

SN74HCT00PWE4

更新时间: 2024-11-20 05:04:47
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
12页 404K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN74HCT00PWE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.12系列:HCT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:25 ns传播延迟(tpd):25 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

SN74HCT00PWE4 数据手册

 浏览型号SN74HCT00PWE4的Datasheet PDF文件第2页浏览型号SN74HCT00PWE4的Datasheet PDF文件第3页浏览型号SN74HCT00PWE4的Datasheet PDF文件第4页浏览型号SN74HCT00PWE4的Datasheet PDF文件第5页浏览型号SN74HCT00PWE4的Datasheet PDF文件第6页浏览型号SN74HCT00PWE4的Datasheet PDF文件第7页 
SN54HCT00, SN74HCT00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCLS062D – NOVEMBER 1988 – REVISED AUGUST 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Typical t = 10 ns  
pd  
4-mA Output Drive at 5 V  
Low Power Consumption, 20-µA Max I  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
CC  
SN54HCT00 . . . J OR W PACKAGE  
SN74HCT00 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HCT00 . . . FK PACKAGE  
(TOP VIEW)  
1A  
1B  
V
CC  
13 4B  
1
2
3
4
5
6
7
14  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
12  
11  
10  
9
1Y  
4A  
4Y  
3B  
3A  
3Y  
17  
16  
2A  
2B  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
2Y  
3B  
8
GND  
NC – No internal connection  
description/ordering information  
These devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A B or  
Y = A + B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HCT00N  
SN74HCT00N  
SN74HCT00D  
SN74HCT00DR  
SN74HCT00DT  
SN74HCT00NSR  
SN74HCT00DBR  
SN74HCT00PW  
SN74HCT00PWR  
SN74HCT00PWT  
SNJ54HCT00J  
SNJ54HCT00W  
SNJ54HCT00FK  
HCT00  
–40°C to 85°C  
SOP – NS  
HCT00  
HT00  
SSOP – DB  
TSSOP – PW  
HT00  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HCT00J  
SNJ54HCT00W  
SNJ54HCT00FK  
–55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74HCT00PWE4 替代型号

型号 品牌 替代类型 描述 数据表
MM74HCT00MTC FAIRCHILD

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