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SN74HC595NSRE4 PDF预览

SN74HC595NSRE4

更新时间: 2024-02-07 12:33:16
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器输出元件
页数 文件大小 规格书
25页 846K
描述
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

SN74HC595NSRE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.02其他特性:PARALLEL OUTPUT IS REGISTERED; UNREGISTERED SERIAL SHIFT RIGHT OUTPUT
计数方向:RIGHT系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:10.2 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):250 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.3 mm
最小 fmax:29 MHzBase Number Matches:1

SN74HC595NSRE4 数据手册

 浏览型号SN74HC595NSRE4的Datasheet PDF文件第4页浏览型号SN74HC595NSRE4的Datasheet PDF文件第5页浏览型号SN74HC595NSRE4的Datasheet PDF文件第6页浏览型号SN74HC595NSRE4的Datasheet PDF文件第8页浏览型号SN74HC595NSRE4的Datasheet PDF文件第9页浏览型号SN74HC595NSRE4的Datasheet PDF文件第10页 
SN54HC595  
SN74HC595  
www.ti.com  
SCLS041H DECEMBER 1982REVISED NOVEMBER 2009  
TIMING REQUIREMENTS  
over operating free-air temperature range (unless otherwise noted)  
TA = 25°C  
SN54HC595  
SN74HC595  
VCC  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
2 V  
4.5 V  
6 V  
6
31  
36  
4.2  
21  
25  
5
fclock  
Clock frequency  
Pulse duration  
25 MHz  
29  
2 V  
80  
16  
14  
80  
16  
14  
100  
20  
17  
75  
15  
13  
50  
10  
9
120  
24  
20  
120  
24  
20  
150  
30  
25  
113  
23  
19  
75  
15  
13  
75  
15  
13  
0
100  
20  
17  
100  
20  
17  
125  
25  
21  
94  
19  
16  
65  
13  
11  
60  
12  
11  
0
SRCLK or RCLK high or low  
SRCLR low  
4.5 V  
6 V  
tw  
ns  
2 V  
4.5 V  
6 V  
2 V  
SER before SRCLK↑  
4.5 V  
6 V  
2 V  
SRCLKbefore RCLK(1)  
SRCLR low before RCLK↑  
SRCLR high (inactive) before SRCLK↑  
4.5 V  
6 V  
tsu  
Setup time  
ns  
2 V  
4.5 V  
6 V  
2 V  
50  
10  
9
4.5 V  
6 V  
2 V  
0
th  
Hold time, SER after SRCLK↑  
4.5 V  
6 V  
0
0
0
ns  
0
0
0
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case  
the shift register is one clock pulse ahead of the storage register.  
Copyright © 1982–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
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Product Folder Link(s): SN54HC595 SN74HC595  

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