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SN74HC377N PDF预览

SN74HC377N

更新时间: 2024-11-22 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 触发器时钟
页数 文件大小 规格书
13页 425K
描述
OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN74HC377N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:0.81
其他特性:WITH HOLD MODE系列:HC/UH
JESD-30 代码:R-PDIP-T20JESD-609代码:e4
长度:24.33 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.0052 A位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:40 ns传播延迟(tpd):200 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.35 mm
最小 fmax:23 MHzBase Number Matches:1

SN74HC377N 数据手册

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SCLS307B– JANUARY 1996 – REVISED JANUARY 2003  
SN54HC377 . . . J OR W PACKAGE  
SN74HC377 . . . DW, N, OR NS PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
CC  
CLKEN  
1Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Typical t = 12 ns  
pd  
±4-mA Output Drive at 5 V  
1D  
Low Input Current of 1 µA Max  
Eight Flip-Flops With Single-Rail Outputs  
2D  
17 7D  
16 7Q  
15 6Q  
2Q  
3Q  
Clock Enable Latched to Avoid False  
Clocking  
3D  
14  
6D  
4D  
13 5D  
12 5Q  
11 CLK  
D
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
4Q  
GND 10  
– Pattern Generators  
SN54HC377 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
These devices are positive-edge-triggered octal  
D-type flip-flops with an enable input. The ’HC377  
devices are similar to the ’HC273 devices, but  
feature a latched clock-enable (CLKEN) input  
instead of a common clear.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK) pulse, if CLKEN is low. Clock triggering  
occurs at a particular voltage level and is not  
directly related to the transition time of the  
positive-going pulse. When CLK is at either the  
high or low level, the D input has no effect at the  
output. These devices are designed to prevent  
false clocking by transitions at CLKEN.  
15 6Q  
14  
6D  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74HC377N  
SN74HC377N  
Tube  
SN74HC377DW  
SN74HC377DWR  
SN74HC377NSR  
SNJ54HC377J  
SNJ54HC377W  
SNJ54HC377FK  
–40°C to 85°C  
SOIC – DW  
HC377  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
CDIP – J  
HC377  
SNJ54HC377J  
SNJ54HC377W  
SNJ54HC377FK  
CFP – W  
LCCC – FK  
Tube  
–55°C to 125°C  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢉ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢓ ꢌꢎ ꢐꢗ ꢒ ꢎꢆꢰꢂ ꢆꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
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ꢠꢭ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢉ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢈ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74HC377N 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC377NE4 TI

类似代替

OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
74HC377D NXP

功能相似

Octal D-type flip-flop with data enable; positive-edge trigger

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SN74HC377NSR TI

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SN74HC377NSRG4 TI

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SN74HC378 TI

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OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN74HC378D TI

获取价格

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE