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SN74HC161PWRG4 PDF预览

SN74HC161PWRG4

更新时间： 2024-11-26 15:52:15
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
29页 1024K
描述
Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, GREEN, PLASTIC, TSSOP-16

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中文翻译

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SN74HC161PWRG4 技术参数

生命周期：Contact Manufacturer包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.57其他特性：RCO OUTPUT
计数方向：UP系列：HC/UH
JESD-30 代码：R-PDSO-G16长度：5 mm
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：255 ns座面最大高度：1.2 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：29 MHz
Base Number Matches：1

SN74HC161PWRG4 数据手册

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SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003  
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D
D
D
D
D
Low Input Current of 1 µA Max  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
Synchronously Programmable  
SN54HC161 . . . J OR W PACKAGE  
SN74HC161 . . . D, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HC161 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLR  
CLK  
A
V
CC  
RCO  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
Q
Q
Q
Q
A
B
C
D
17  
16  
15  
14  
B
C
D
NC  
C
NC  
Q
Q
C
D
D
ENP  
GND  
ENT  
LOAD  
9 10 11 12 13  
NC − No internal connection  
description/ordering information  
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed  
counting designs. The ’HC161 devices are 4-bit binary counters. Synchronous operation is provided by having  
all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed  
by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output  
counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK)  
input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC161N  
SN74HC161N  
SN74HC161D  
SN74HC161DR  
SN74HC161DT  
SN74HC161NSR  
SN74HC161PW  
SN74HC161PWR  
SN74HC161PWT  
SNJ54HC161J  
SNJ54HC161W  
SNJ54HC161FK  
SOIC − D  
SOP − NS  
HC161  
HC161  
−40°C to 85°C  
TSSOP − PW  
HC161  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC161J  
SNJ54HC161W  
SNJ54HC161FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...29

中文翻译

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