SN74F657DWR

更新时间： 2024-09-30 22:53:35

品牌	Logo	应用领域
德州仪器 - TI		逻辑集成电路光电二极管输出元件
页数	文件大小	规格书
10页	229K
描述
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS

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SN74F657DWR 数据手册

SN74F657

OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER

AND 3-STATE OUTPUTS

SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993

DW OR NT PACKAGE

• Combines ′F245 and ′F280B Functions in

(TOP VIEW)

One Package

• High-Impedance N-P-N Inputs for Reduced

Loading (70 µA in Low and High States)

T/R

GND

• High Output Drive and Light Bus Loading

• 3-State B Outputs Sink 64 mA and Source

15 mA

• Input Diodes for Termination Effects

• Package Options Include Plastic

Small-Outline Packages and Standard

Plastic 300-mil DIPs

A8 10

15 B7

ODD/EVEN

ERR

PARITY

description

The SN74F657 contains eight noninverting

buffers with 3-state outputs and an 8-bit parity

generator/checker. It is intended for bus-oriented

applications. The buffers have a specified current

sinking capability of 24 mA at the A port and 64 mA

at the B port.

The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers.

When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port

from the B port.

When the output enable (OE) input is high, both the A and B ports are placed in a high-impedance state

(disabled). The ODD/EVEN input allows the user to select between odd or even parity systems. When

transmitting from A port to B port (T/R high), PARITY is an output from the generator/checker. When receiving

from B port to A port (T/R low), PARITY is an input.

When transmitting (T/Rhigh), theparityselect(ODD/EVEN) input is made high or low as appropriate. The A port

is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by

ODD/EVEN and the number of high bits on A port. When ODD/EVEN is low (for even parity) and the number

of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port

is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R low), the B port is polled to determine the number of high bits. If ODD/EVEN

is low (for even parity) and the number of highs on B port is:

1. Odd and the PARITY input is high, then ERR will be high signifying no error.

2. Even and the PARITY input is high, then ERR will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

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SN74F657DWR 替代型号

型号	品牌	替代类型	描述	数据表
SN74F657DWE4	TI	完全替代	F/FAST SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOIC-24
SN74F657DWG4	TI	完全替代	F/FAST SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOIC-24

与SN74F657DWR相关器件

型号	品牌	获取价格	描述	数据表
SN74F657DWRE4	TI	获取价格	F/FAST SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOIC-24
SN74F657DWRG4	TI	获取价格	F/FAST SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOIC-24
SN74F657NT	TI	获取价格	OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SN74F657NT-10	TI	获取价格	F/FAST SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24
SN74F657NTE4	ROCHESTER	获取价格	Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDIP24, 0.300 INCH, PLAST
SN74F657NTE4	TI	获取价格	Octal Transceiver With Parity Generator/Checker and 3-State Outputs 24-PDIP 0 to 70
SN74F74	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74F74D	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74F74D-00	TI	获取价格	F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
SN74F74D-00R	TI	获取价格	F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14

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