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SN74F657NT-10

更新时间： 2024-09-24 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 240K
描述
F/FAST SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24

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中文翻译

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SN74F657NT-10 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknown风险等级：5.39
其他特性：WITH DIRECTION CONTROL; PARITY GENERATION A TO B; ERROR DETECTION B TO A系列：F/FAST
JESD-30 代码：R-PDIP-T24长度：31.64 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：8 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN74F657NT-10 数据手册

 浏览型号SN74F657NT-10的Datasheet PDF文件第2页浏览型号SN74F657NT-10的Datasheet PDF文件第3页浏览型号SN74F657NT-10的Datasheet PDF文件第4页浏览型号SN74F657NT-10的Datasheet PDF文件第5页浏览型号SN74F657NT-10的Datasheet PDF文件第6页浏览型号SN74F657NT-10的Datasheet PDF文件第7页 
SN74F657  
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER  
AND 3-STATE OUTPUTS  
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993  
DW OR NT PACKAGE  
• Combines ′F245 and ′F280B Functions in  
(TOP VIEW)  
One Package  
• High-Impedance N-P-N Inputs for Reduced  
Loading (70 µA in Low and High States)  
T/R  
A1  
A2  
A3  
A4  
A5  
OE  
B1  
B2  
B3  
B4  
GND  
GND  
B5  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
• High Output Drive and Light Bus Loading  
• 3-State B Outputs Sink 64 mA and Source  
15 mA  
• Input Diodes for Termination Effects  
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
V
CC  
A6  
A7  
B6  
A8 10  
15 B7  
ODD/EVEN  
ERR  
B8  
PARITY  
11  
12  
14  
13  
description  
The SN74F657 contains eight noninverting  
buffers with 3-state outputs and an 8-bit parity  
generator/checker. It is intended for bus-oriented  
applications. The buffers have a specified current  
sinking capability of 24 mA at the A port and 64 mA  
at the B port.  
The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers.  
When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port  
from the B port.  
When the output enable (OE) input is high, both the A and B ports are placed in a high-impedance state  
(disabled). The ODD/EVEN input allows the user to select between odd or even parity systems. When  
transmitting from A port to B port (T/R high), PARITY is an output from the generator/checker. When receiving  
from B port to A port (T/R low), PARITY is an input.  
When transmitting (T/Rhigh), theparityselect(ODD/EVEN) input is made high or low as appropriate. The A port  
is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by  
ODD/EVEN and the number of high bits on A port. When ODD/EVEN is low (for even parity) and the number  
of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port  
is even, the PARITY will be low, keeping even parity.  
When in the receive mode (T/R low), the B port is polled to determine the number of high bits. If ODD/EVEN  
is low (for even parity) and the number of highs on B port is:  
1. Odd and the PARITY input is high, then ERR will be high signifying no error.  
2. Even and the PARITY input is high, then ERR will be low indicating an error.  
The SN74F657 is characterized for operation from 0°C to 70°C.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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