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SN74CBT16211CDLRG4 PDF预览

SN74CBT16211CDLRG4

更新时间: 2024-11-28 04:11:47
品牌 Logo 应用领域
德州仪器 - TI 开关
页数 文件大小 规格书
14页 246K
描述
24-BIT FET BUS SWITCH 5-V BUS SWITCH WITH 2-V UNDERSHOOT PROTECTION

SN74CBT16211CDLRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP56,.4针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.16其他特性:DUMMY VAL
系列:CBT/FST/QS/5C/BJESD-30 代码:R-PDSO-G56
JESD-609代码:e4长度:18.415 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:12功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):0.24 ns
认证状态:Not Qualified座面最大高度:2.79 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.49 mmBase Number Matches:1

SN74CBT16211CDLRG4 数据手册

 浏览型号SN74CBT16211CDLRG4的Datasheet PDF文件第2页浏览型号SN74CBT16211CDLRG4的Datasheet PDF文件第3页浏览型号SN74CBT16211CDLRG4的Datasheet PDF文件第4页浏览型号SN74CBT16211CDLRG4的Datasheet PDF文件第5页浏览型号SN74CBT16211CDLRG4的Datasheet PDF文件第6页浏览型号SN74CBT16211CDLRG4的Datasheet PDF文件第7页 
ꢉ ꢃ ꢊꢅꢋ ꢆ ꢌ ꢍꢆ ꢅꢎꢀ ꢀ ꢏꢋ ꢆꢄ  
SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Member of the Texas Instruments  
WidebusFamily  
Undershoot Protection for Off-Isolation on  
A and B Ports Up To −2 V  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
1A1  
1A2  
1A3  
1A4  
1A5  
1A6  
GND  
1A7  
1A8  
1A9  
1A10  
1A11  
1A12  
2A1  
2A2  
1OE  
2OE  
1B1  
1B2  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
1B9  
1B10  
1B11  
1B12  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
2B7  
2B8  
2B9  
2B10  
2B11  
2B12  
2
Bidirectional Data Flow, With Near-Zero  
Propagation Delay  
3
4
5
Low ON-State Resistance (r  
)
on  
Characteristics (r = 3 Typical)  
6
on  
7
Low Input/Output Capacitance Minimizes  
Loading and Signal Distortion  
8
9
(C  
= 5.5 pF Typical)  
io(OFF)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
D
D
Data and Control Inputs Provide  
Undershoot Clamp Diodes  
Low Power Consumption  
(I  
= 3 µA Max)  
CC  
D
V
Operating Range From 4 V to 5.5 V  
CC  
D
Data I/Os Support 0 to 5-V Signaling Levels  
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)  
V
CC  
2A3  
GND  
2A4  
2A5  
2A6  
2A7  
2A8  
2A9  
D
D
D
D
Control Inputs Can Be Driven by TTL or  
5-V/3.3-V CMOS Outputs  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
2A10  
2A11  
2A12  
− 1000-V Charged-Device Model (C101)  
D
Supports Both Digital and Analog  
Applications: PCI Interface, Memory  
Interleaving, Bus Isolation, Low-Distortion  
Signal Gating  
NC − No internal connection  
description/ordering information  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74CBT16211CDL  
SN74CBT16211CDLR  
SN74CBT16211CDGG  
SN74CBT16211CDGGR  
SN74CBT16211CDGVR  
SSOP − DL  
CBT16211C  
Tape and reel  
Tube  
−40°C to 85°C  
TSSOP − DGG  
TVSOP − DGV  
CBT16211C  
CY211C  
Tape and reel  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢆꢤ  
Copyright 2003, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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