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SN74AS885FN-00 PDF预览

SN74AS885FN-00

更新时间： 2024-10-02 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 输入元件输出元件逻辑集成电路
页数 文件大小 规格书
19页 711K
描述
AS SERIES, 8-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PQCC28

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SN74AS885FN-00 技术参数

生命周期：Obsolete包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.75其他特性：B PORT WITH STANDARD INPUTS; WITH ARITHMETIC COMPARISON; WITH A < B & A > B OUTPUTS
系列：ASJESD-30 代码：S-PQCC-J28
长度：11.5062 mm负载电容（CL）：50 pF
逻辑集成电路类型：MAGNITUDE COMPARATOR位数：8
功能数量：1端子数量：28
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER最大电源电流（ICC）：210 mA
传播延迟（tpd）：15 ns认证状态：Not Qualified
座面最大高度：4.57 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：11.5062 mmBase Number Matches：1

SN74AS885FN-00 数据手册

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SN54AS885, SN74AS885  
8-BIT MAGNITUDE COMPARATORS  
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995  
SN54AS885 . . . JT PACKAGE  
SN74AS885 . . . DW OR NT PACKAGE  
(TOP VIEW)  
• Latchable P-Input Ports With Power-Up  
Clear  
• Choice of Logical or Arithmetic  
(Two’s Complement) Comparison  
L/A  
P < QIN  
P > QIN  
Q7  
V
CC  
23 PLE  
1
2
3
4
5
6
7
8
9
24  
• Data and PLE Inputs Utilize pnp Input  
Transistors to Reduce dc Loading Effects  
22 P7  
21 P6  
• Approximately 35% Improvement in  
ac Performance Over Schottky TTL While  
Performing More Functions  
Q6  
Q5  
Q4  
Q3  
20 P5  
19 P4  
18 P3  
• Cascadable to n Bits While Maintaining  
17 P2  
High Performance  
Q2  
16 P1  
• 10% Less Power Than STTL for an 8-Bit  
Q1 10  
Q0 11  
15 P0  
Comparison  
14 P < QOUT  
13 P > QOUT  
• Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
(NT) and Ceramic (JT) 300-mil DIPs  
GND 12  
SN54AS885 . . . FK PACKAGE  
(TOP VIEW)  
description  
These advanced Schottky devices are capable of  
performing high-speed arithmetic or logic  
comparisons on two 8-bit binary or two’s  
complement words. Two fully decoded decisions  
about words P and Q are externally available at  
two outputs. These devices are fully expandable  
to any number of bits without external gates. To  
compare words of longer lengths, the P > QOUT  
and P < QOUT outputs of a stage handling less  
significant bits can be connected to the P > QIN  
and P < QIN inputs of the next stage handling  
more significant bits. The cascading paths are  
implemented with only a two-gate-level delay to  
reduce overall comparison times for long words.  
Two alternative methods of cascading are shown  
in application information.  
4
3
2
1
28 27 26  
25  
Q7  
Q6  
Q5  
NC  
Q4  
Q3  
Q2  
P6  
P5  
P4  
NC  
P3  
P2  
P1  
5
24  
23  
22  
21  
20  
19  
6
7
8
9
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
The latch is transparent when P latch-enable  
(PLE) input is high; the P-input port is latched  
when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry  
is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE,  
P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically  
–0.25 mA, which minimizes dc loading effects.  
The SN54AS885 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74AS885 is characterized for operation from 0°C to 70°C.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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