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SN74AS580N3 PDF预览

SN74AS580N3

更新时间: 2024-11-15 14:28:27
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
19页 857K
描述
AS SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP20

SN74AS580N3 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.88
Is Samacsys:N其他特性:BROADSIDE VERSION OF 533
系列:ASJESD-30 代码:R-PDIP-T20
长度:24.325 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):106 mA传播延迟(tpd):8 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN74AS580N3 数据手册

 浏览型号SN74AS580N3的Datasheet PDF文件第2页浏览型号SN74AS580N3的Datasheet PDF文件第3页浏览型号SN74AS580N3的Datasheet PDF文件第4页浏览型号SN74AS580N3的Datasheet PDF文件第5页浏览型号SN74AS580N3的Datasheet PDF文件第6页浏览型号SN74AS580N3的Datasheet PDF文件第7页 
ꢌ ꢍꢎꢄꢅꢊꢏ ꢐꢎꢑ ꢒꢓꢊ ꢎ ꢔꢄꢁꢀꢒꢄꢔꢓ ꢁꢎ ꢊꢅꢄꢎꢍ ꢕ ꢓ  
SDAS277 − JANUARY 1995  
SN54ALS580B . . . J OR W PACKAGE  
SN74ALS580B, SN74AS580 . . . DW OR N PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
Bus-Structured Pinout  
Inverting-Logic Outputs  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs, and Ceramic Flat  
(W) Packages  
description  
13 7Q  
12 8Q  
These octal D-type transparent latches feature  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
11  
GND  
LE  
SN54ALS580B . . . FK PACKAGE  
(TOP VIEW)  
While the latch-enable (LE) input is high, outputs  
(Q) respond to the data (D) inputs. When LE is low,  
the outputs are latched to retain the data that was  
set up.  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or a high-impedance state. In  
the high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and the increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
9 10 11 12 13  
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
The SN54ALS580B is characterized for operation over the full military temperature range of 55°C to 125°C.  
The SN74ALS580B and SN74AS580 are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
ꢎꢥ  
Copyright 1995, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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