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SN74AS286N PDF预览

SN74AS286N

更新时间: 2024-11-13 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器
页数 文件大小 规格书
8页 127K
描述
9-BIT PARITY GENERATORS/CHECKERS WITH BUS-DRIVER PARITY I/O PORT

SN74AS286N 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.39其他特性:EVEN PARITY GENERATOR; ODD/EVEN PARITY CHECKER; WITH PARITY I/O AND ACTIVE LOW PARITY ERROR OUTPUT
系列:ASJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.3 mm
负载电容(CL):50 pF逻辑集成电路类型:PARITY GENERATOR/CHECKER
最大I(ol):0.048 A位数:9
功能数量:1端子数量:14
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):50 mAProp。Delay @ Nom-Sup:16.5 ns
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Arithmetic Circuit
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.35 mm
Base Number Matches:1

SN74AS286N 数据手册

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SN54AS286, SN74AS286  
9-BIT PARITY GENERATORS/CHECKERS  
WITH BUS-DRIVER PARITY I/O PORT  
SDAS050B – DECEMBER 1983 – REVISED DECEMBER 1994  
SN54AS286 . . . J PACKAGE  
SN74AS286 . . . D OR N PACKAGE  
(TOP VIEW)  
Generate Either Odd or Even Parity for  
Nine Data Lines  
Cascadable for n-Bit Parity  
Direct Bus Connection for Parity  
Generation or Checking by Using the  
Parity I/O Port  
G
H
V
F
E
D
C
B
A
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
XMIT  
I
PARITY ERROR  
PARITY I/O  
GND  
Glitch-Free Bus During Power Up/Down  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
8
SN54AS286 . . . FK PACKAGE  
(TOP VIEW)  
description  
The SN54AS286 and SN74AS286 universal 9-bit  
parity generators/checkers feature a local output  
for parity checking and a 48-mA bus-driving  
parity input/output (I/O) port for parity  
generation/checking. The word-length capability  
is easily expanded by cascading.  
3
2
1
20 19  
18  
E
XMIT  
4
5
6
7
8
NC  
D
NC  
17  
16  
15  
14  
I
NC  
NC  
C
The transmit (XMIT) control input is implemented  
specifically to accommodate cascading. When  
XMIT is low, the parity tree is disabled and  
PARITY ERROR remains at a high logic level  
regardless of the input levels. When XMIT is high,  
the parity tree is enabled. PARITY ERROR  
indicates a parity error when either an even  
number of inputs (A–I) are high and PARITY I/O  
is forced to a low logic level, or when an odd  
number of inputs are high and PARITY I/O is  
forced to a high logic level.  
PARITY ERROR  
9 10 11 12 13  
NC – No internal connection  
The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up  
or power down to prevent bus glitches.  
The SN54AS286 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74AS286 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
NUMBER OF INPUTS  
PARITY  
I/O  
PARITY  
ERROR  
(AI) THAT  
ARE HIGH  
XMIT  
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
l
H
L
h
l
H
H
H
L
l
h
h
h
h
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
h
l
L
H
h = high input level  
H = high output level  
l = low input level  
L = low output level  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AS286N 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS286D TI

完全替代

9-BIT PARITY GENERATORS/CHECKERS WITH BUS-DRIVER PARITY I/O PORT

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