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SN74AS280NSRE4 PDF预览

SN74AS280NSRE4

更新时间: 2024-09-25 22:21:23
品牌 Logo 应用领域
德州仪器 - TI 运算电路逻辑集成电路光电二极管
页数 文件大小 规格书
12页 345K
描述
9-BIT PARITY GENERATORS/CHECKERS

SN74AS280NSRE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, SOP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.45Is Samacsys:N
其他特性:ODD/EVEN PARITY GENERATOR系列:AS
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:10.2 mm逻辑集成电路类型:PARITY GENERATOR/CHECKER
湿度敏感等级:1位数:9
功能数量:1端子数量:14
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):12 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

SN74AS280NSRE4 数据手册

 浏览型号SN74AS280NSRE4的Datasheet PDF文件第2页浏览型号SN74AS280NSRE4的Datasheet PDF文件第3页浏览型号SN74AS280NSRE4的Datasheet PDF文件第4页浏览型号SN74AS280NSRE4的Datasheet PDF文件第5页浏览型号SN74AS280NSRE4的Datasheet PDF文件第6页浏览型号SN74AS280NSRE4的Datasheet PDF文件第7页 
SN74ALS280, SN74AS280  
9-BIT PARITY GENERATORS/CHECKERS  
SDAS038C – DECEMBER 1982 – REVISED DECEMBER 1994  
D OR N PACKAGE  
(TOP VIEW)  
Generate Either Odd or Even Parity for Nine  
Data Lines  
Cascadable for n-Bit Parity  
G
H
NC  
V
F
E
D
C
B
A
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
Can Be Used to Upgrade Existing Systems  
Using MSI Parity Circuits  
Package Options Include Plastic  
Small-Outline (D) Packages and Standard  
Plastic (N) 300-mil DIPs  
I
Σ EVEN  
Σ ODD  
GND  
8
description  
NC – No internal connection  
These universal 9-bit parity generators/checkers  
utilize advanced Schottky high-performance  
circuitry and feature odd (Σ ODD) and even (Σ EVEN) outputs to facilitate operation of either odd- or even-parity  
applications. The word-length capability is easily expanded by cascading.  
These devices can be used to upgrade the performance of most systems utilizing the SN74ALS180 and  
SN74AS180parity generators/checkers. Although the SN74ALS280 and SN74AS280 are implemented without  
expander inputs, the corresponding function is provided by the availability of an input (I) at terminal 4 and the  
absence of any internal connection at terminal 3. This permits the SN74ALS280 and SN74AS280 to be  
substituted for the SN74ALS180 and SN74AS180 in existing designs to produce an identical function even if  
the devices are mixed with existing SN74ALS180 and SN74AS180 devices.  
All SN74AS280 inputs are buffered to lower the drive requirements.  
The SN74ALS280 and SN74AS280 are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
NO. OF INPUTS  
A–I  
THAT ARE HIGH  
OUTPUTS  
Σ EVEN  
Σ ODD  
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
H
L
L
H
logic symbol  
2k  
8
A
B
C
D
E
F
G
H
I
9
10  
11  
12  
13  
1
5
6
Σ EVEN  
Σ ODD  
2
4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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