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SN74ALS37ANSRG4 PDF预览

SN74ALS37ANSRG4

更新时间: 2024-11-16 14:44:51
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 294K
描述
ALS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, GREEN, PLASTIC, SOP-14

SN74ALS37ANSRG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.82
其他特性:IOH = 2.6MA @ VOH = 2.4V; IOL = 24MA @ VOL = 0.5V系列:ALS
JESD-30 代码:R-PDSO-G14长度:10.2 mm
逻辑集成电路类型:NAND GATE最大I(ol):0.024 A
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):7.8 mA
Prop。Delay @ Nom-Sup:8 ns传播延迟(tpd):8 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

SN74ALS37ANSRG4 数据手册

 浏览型号SN74ALS37ANSRG4的Datasheet PDF文件第2页浏览型号SN74ALS37ANSRG4的Datasheet PDF文件第3页浏览型号SN74ALS37ANSRG4的Datasheet PDF文件第4页浏览型号SN74ALS37ANSRG4的Datasheet PDF文件第5页浏览型号SN74ALS37ANSRG4的Datasheet PDF文件第6页浏览型号SN74ALS37ANSRG4的Datasheet PDF文件第7页 
SN54ALS37A, SN74ALS37A  
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS  
SDAS195A – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS37A . . . J PACKAGE  
SN74ALS37A . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
These devices contain four independent 2-input  
positive-NAND buffers. They perform the Boolean  
functions Y = A B or Y = A + B in positive logic.  
2Y  
GND  
8
The SN54ALS37A is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS37A is characterized for  
operation from 0°C to 70°C.  
SN54ALS37A . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
INPUTS  
OUTPUT  
Y
1Y  
NC  
2A  
4A  
4
5
6
7
8
A
B
H
X
L
NC  
17  
H
L
L
H
H
16 4Y  
15  
14  
NC  
2B  
NC  
3B  
X
9 10 11 12 13  
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
1A  
2
3
1A  
2
&
3
6
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
1B  
4
4
2A  
5
6
8
2A  
5
2B  
9
2B  
9
3A  
3A  
10  
3B  
12  
4A  
13  
4B  
8
10  
3B  
12  
4A  
11  
11  
13  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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