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SN74ALS29825 PDF预览

SN74ALS29825

更新时间: 2024-02-29 23:34:57
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
9页 70K
描述
8-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN74ALS29825 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.68其他特性:CLEAR AND CLOCK ENABLE; TRIPLE OUTPUT ENABLE
系列:ALSJESD-30 代码:R-PDIP-T24
JESD-609代码:e0长度:31.64 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):17.5 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN74ALS29825 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢆ ꢂ ꢉꢊ ꢀꢁꢋ ꢃ ꢄꢅ ꢀ ꢆ ꢇ ꢈ ꢆ ꢂ ꢉꢊ ꢀꢁꢋ ꢃ ꢄꢅ ꢀꢆ ꢇꢈꢆ ꢌ  
ꢈ ꢍ ꢎꢏ ꢐ ꢊꢎꢑ ꢀꢊ ꢏꢁꢐ ꢒꢓꢔꢄꢕꢒ ꢊꢔ ꢅ ꢏꢖꢍ ꢔ ꢅ ꢗ ꢖꢀꢊ ꢘꢏ ꢐ ꢙꢊꢚ ꢍ ꢀ ꢐꢄꢐ ꢒꢊ ꢗꢑ ꢐꢖ ꢑꢐ ꢀ  
SDAS147B — JANUARY 1986 — REVISED MARCH 1990  
SN54ALS29825 . . . JT PACKAGE  
SN74ALS29825 . . . DW OR NT PACKAGE  
Functionally Equivalent to AMD AM29825  
and AM29826  
(TOP VIEW)  
Improved I  
Specifications  
OH  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OC1  
OC2  
1D  
V
CC  
OC3  
Multiple Output Enables Allow Multiuser  
2
Control of the Interface  
3
1Q  
4
2D  
2Q  
Outputs Have Undershoot Protection  
5
3D  
3Q  
Circuitry  
6
4D  
4Q  
7
5D  
5Q  
Power-Up High-Impedance State  
Package Options Include Plastic  
“Small-Outline” Packages and Standard  
Plastic and Ceramic 300-mil DIPs  
8
6D  
6Q  
9
7D  
7Q  
10  
11  
12  
8D  
8Q  
CLR  
GND  
CLKEN  
CLK  
Buffered Control Inputs to Reduce DC  
Loading Effect  
SN74ALS29826 . . . DW OR NT PACKAGE  
(TOP VIEW)  
description  
These 8-bit flip-flops feature three-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing multiuser  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OC1  
OC2  
1D  
V
CC  
OC3  
2
3
1Q  
4
2D  
2Q  
5
3D  
3Q  
6
4D  
4Q  
7
5D  
5Q  
With the clock enable (CLKEN) low, the eight  
D-type edge-triggered flip-flops enter data on the  
low-to- high transitions of the clock. Taking  
CLKEN high will disable the clock buffer, thus  
latching the outputs. The ALS29825 has  
noninverting D inputs and the ALS29826 has  
inverting D inputs. Taking the CLR input low  
causes the eight Q outputs to go low independent-  
ly of the clock.  
8
6D  
6Q  
9
7D  
7Q  
10  
11  
12  
8D  
8Q  
CLR  
GND  
CLKEN  
CLK  
Multiuser buffered output-control inputs (OC1, OC2, and OC3) can be used to place the eight outputs in either  
a normal logic state (high or low level) or a high-impedance state. The outputs are also in the high-impedance  
state during power-up and power-down conditions. The outputs remain in the high-impedance state while the  
device is powered-down. In the high-impedance state the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a  
bus-organized system without need for interface or pullup components. The output controls do not affect the  
internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are  
in the high-impedance state.  
The SN54ALS29825 is characterized over the full military range of − 55°C to 125°C. The SN74ALS29825 and  
SN74ALS29826 are characterized for operation from 0°C to 70°C.  
ꢖꢓ ꢗ ꢛꢑ ꢕ ꢐꢏ ꢗꢁ ꢛ ꢄꢐꢄ ꢜꢝ ꢞ ꢟꢠ ꢡꢢ ꢣꢜꢟ ꢝ ꢜꢤ ꢥꢦ ꢠ ꢠ ꢧꢝꢣ ꢢꢤ ꢟꢞ  
Copyright 1991, Texas Instruments Incorporated  
ꢝꢟꢣ  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
1

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