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SN74ALS259FN-00 PDF预览

SN74ALS259FN-00

更新时间： 2024-11-19 14:07:19
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
17页 651K
描述
ALS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PQCC20

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SN74ALS259FN-00 技术参数

生命周期：Obsolete包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.69其他特性：1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH
系列：ALSJESD-30 代码：S-PQCC-J20
长度：8.9662 mm逻辑集成电路类型：D LATCH
位数：1功能数量：1
端子数量：20最高工作温度：70 °C
最低工作温度：输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
认证状态：Not Qualified座面最大高度：4.57 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD触发器类型：LOW LEVEL
宽度：8.9662 mmBase Number Matches：1

SN74ALS259FN-00 数据手册

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SDAS217A − DECEMBER 1982 − REVISED DECEMBER 1994  
SN54ALS259 . . . J PACKAGE  
SN74ALS259 . . . D OR N PACKAGE  
(TOP VIEW)  
• 8-Bit Parallel-Out Storage Register  
Performs Serial-to-Parallel Conversion With  
Storage  
• Asynchronous Parallel Clear  
• Active-High Decoder  
S0  
S1  
S2  
Q0  
Q1  
Q2  
Q3  
GND  
V
CC  
CLR  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
• Enable/Disable Input Simplifies Expansion  
• Expandable for n-Bit Applications  
• Four Distinct Functional Modes  
G
D
Q7  
Q6  
Q5  
Q4  
• Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
SN54ALS259 . . . FK PACKAGE  
(TOP VIEW)  
description  
These 8-bit addressable latches are designed for  
general-purpose storage applications in digital  
systems. Specific uses include working registers,  
serial-holding registers, and active-high decoders  
or demultiplexers. They are multifunctional  
devices capable of storing single-line data in eight  
addressable latches and being a 1-of-8 decoder or  
demultiplexer with active-high outputs.  
3
2
1 20 19  
18  
S2  
Q0  
NC  
Q1  
Q2  
G
4
5
6
7
8
17  
16  
15  
14  
D
NC  
Q7  
Q6  
9 10 11 12 13  
Four distinct modes of operation are selectable by  
controlling the clear (CLR) and enable (G) inputs  
as shown in the function table. In the  
addressable-latch mode, data at the data-in  
terminal is written into the addressed latch. The  
NC − No internal connection  
addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the  
memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To  
eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the  
address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the  
level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address  
and data inputs.  
The SN54ALS259 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74ALS259 is characterized for operation from 0°C to 70°C.  
Function Tables  
FUNCTION  
OUTPUT OF  
EACH  
INPUTS  
ADDRESSED OTHER  
FUNCTION  
CLR  
G
LATCH  
OUTPUT  
H
H
L
L
H
L
D
Q
Q
Addressable latch  
Memory  
iO  
iO  
Q
iO  
D
L
8-line demultiplexer  
Clear  
L
H
L
L
D = the level at the data input.  
= the level of Q (i = Q, 1, . . . 7 as appropriate) before the indicated  
Q
iO  
i
steady-state input conditions were established.  
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Copyright 1994, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...17

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