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SN74ALS1034N-10 PDF预览

SN74ALS1034N-10

更新时间: 2024-11-20 21:01:31
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
19页 1075K
描述
ALS SERIES, HEX 1-INPUT NON-INVERT GATE, PDIP14

SN74ALS1034N-10 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.23系列:ALS
JESD-30 代码:R-PDIP-T14长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:BUFFER
功能数量:6输入次数:1
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE最大电源电流(ICC):14 mA
传播延迟(tpd):8 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN74ALS1034N-10 数据手册

 浏览型号SN74ALS1034N-10的Datasheet PDF文件第2页浏览型号SN74ALS1034N-10的Datasheet PDF文件第3页浏览型号SN74ALS1034N-10的Datasheet PDF文件第4页浏览型号SN74ALS1034N-10的Datasheet PDF文件第5页浏览型号SN74ALS1034N-10的Datasheet PDF文件第6页浏览型号SN74ALS1034N-10的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢈ ꢃ ꢉꢊ ꢀꢁꢂ ꢃ ꢄꢀꢆ ꢇ ꢈ ꢃ ꢄꢉꢊꢀ ꢁꢋ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢈꢃ ꢉ ꢊꢀ ꢁ ꢋꢃ ꢄꢀ ꢆ ꢇꢈꢃꢄ  
ꢌꢍꢎ ꢊ ꢏꢐ ꢑ ꢒꢍ ꢐ ꢀ  
SDAS053B − APRIL 1982 − REVISED JANUARY 1995  
SN54ALS1034, SN54AS1034A . . . J PACKAGE  
SN74ALS1034, SN74AS1034A . . . D OR N PACKAGE  
(TOP VIEW)  
AS1034A Offer High Capacitive-Drive  
Capability  
Noninverting Drivers  
Package Options Include Plastic  
1A  
1Y  
2A  
2Y  
3A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
6A  
6Y  
5A  
5Y  
4A  
4Y  
description  
3Y  
GND  
8
These devices contain six independent  
noninverting drivers. They perform the Boolean  
function Y = A.  
SN54ALS1034, SN54AS1034A . . . FK PACKAGE  
(TOP VIEW)  
The SN54ALS1034 and SN54AS1034A are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS1034  
and  
SN74AS1034A  
are  
3
2
1
20 19  
18  
2A  
NC  
2Y  
4
5
6
7
8
6Y  
NC  
5A  
NC  
5Y  
characterized for operation from 0°C to 70°C.  
17  
16  
15  
14  
FUNCTION TABLE  
(each buffer)  
NC  
3A  
INPUT  
A
OUTPUT  
Y
9 10 11 12 13  
H
L
H
L
NC − No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1A  
3
2
4
1
2
4
6
8
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
1A  
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
2A  
5
6
3
3A  
9
2A  
8
4A  
11  
10  
12  
5
5A  
13  
3A  
6A  
9
4A  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
11  
10  
5A  
13  
12  
6A  
ꢗꢣ  
Copyright 1995, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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