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SN74AHC273PWLE PDF预览

SN74AHC273PWLE

更新时间: 2024-11-19 02:58:23
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德州仪器 - TI /
页数 文件大小 规格书
18页 585K
描述
Octal D-Type Flip-Flops With Clear

SN74AHC273PWLE 数据手册

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SN54AHC273, SN74AHC273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS376G – JUNE 1997 – REVISED JULY 2003  
SN54AHC273 . . . J OR W PACKAGE  
SN74AHC273 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Operating Range 2-V to 5.5-V V  
CC  
Contain Eight Flip-Flops With Single-Rail  
Outputs  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
Direct Clear Input  
Individual Data Input to Each Flip-Flop  
18 8D  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
17  
16  
15  
14  
13  
12  
11  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
– Pattern Generators  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
GND  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
SN54AHC273 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
These circuits are positive-edge-triggered D-type  
flip-flops with a direct clear (CLR) input.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
17 7D  
4
5
6
7
8
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a  
particular voltage level and is not directly related  
to the transition time of the positive-going pulse.  
When CLK is at either the high or low level, the  
D input has no effect at the output.  
16  
15  
14  
7Q  
6Q  
6D  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHC273N  
SN74AHC273N  
Tube  
SN74AHC273DW  
SN74AHC273DWR  
SN74AHC273NSR  
SN74AHC273DBR  
SN74AHC273PW  
SN74AHC273PWR  
SOIC – DW  
AHC273  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
AHC273  
HA273  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HA273  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
SN74AHC273DGVR  
SNJ54AHC273J  
HA273  
SNJ54AHC273J  
SNJ54AHC273W  
SNJ54AHC273FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHC273W  
SNJ54AHC273FK  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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