ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢉ ꢊ
ꢀꢋ ꢁꢈ ꢌ ꢍ ꢎꢏꢀ ꢎꢏꢐ ꢐ ꢍ ꢑ ꢈ ꢄꢒꢍ
ꢓ ꢋꢒ ꢅ ꢔ ꢕꢀꢒꢄꢒ ꢍ ꢖ ꢏꢒ ꢗꢏ ꢒ
SCLS379J − AUGUST 1997 − REVISED JUNE 2005
D
D
D
Operating Range of 2 V to 5.5 V
D
D
8-mA Output Drive at 5 V
Max t of 6 ns at 5 V
pd
Low Power Consumption, 10-µA Max I
Latch-Up Performance Exceeds 250 mA Per
JESD 17
CC
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
OE
V
Y
1
2
3
5
1
2
3
5
OE
A
V
Y
CC
CC
1
2
3
5
4
OE
A
V
Y
CC
A
4
GND
4
GND
GND
See mechanical drawings for dimensions.
description/ordering information
The SN74AHC1G126 is a single bus buffer gate/line driver with 3-state output. The output is disabled when the
output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
SN74AHC1G126DBVR
SN74AHC1G126DBVT
SN74AHC1G126DCKR
SN74AHC1G126DCKT
SN74AHC1G126DRLR
SOT (SOT-23) – DBV
A26_
−40°C to 85°C
SOT (SC-70) – DCK
AN_
AN_
SOT (SOT-553) – DRL
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
H
L
H
H
L
H
L
X
Z
logic diagram (positive logic)
1
2
OE
A
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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