ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢃ
ꢀꢊ ꢁꢈ ꢋ ꢌ ꢊꢁ ꢍꢌꢎ ꢏꢌ ꢎ ꢈ ꢄꢏꢌ
SCLS318Q − MARCH 1996 − REVISED JUNE 2005
D
D
D
D
Operating Range of 2 V to 5.5 V
D
D
Schmitt Trigger Action at All Inputs Makes
the Circuit Tolerant for Slower Input Rise
and Fall Time
Max t of 6.5 ns at 5 V
pd
Low Power Consumption, 10-µA Max I
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
8-mA Output Drive at 5 V
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
1
2
3
5
NC
V
Y
1
2
3
5
4
NC
A
V
Y
CC
CC
1
2
3
5
4
NC
A
V
Y
CC
A
4
GND
GND
GND
NC – No internal connection
See mechanical drawings for dimensions.
description/ordering information
The SN74AHC1G04 contains one inverter gate. The device performs the Boolean function Y = A.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
Reel of 3000
Reel of 250
Reel of 3000
SN74AHC1G04DBVR
SN74AHC1G04DBVT
SN74AHC1G04DCKR
SOT (SOT-23) − DBV
A04_
−40°C to 85°C
SOT (SC-70) − DCK
AC_
AC_
Reel of 250
SN74AHC1G04DCKT
SN74AHC1G04DRLR
SOT (SOT-553) – DRL
Reel of 4000
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
2
4
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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