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SN74AC240DWE4 PDF预览

SN74AC240DWE4

更新时间： 2024-11-18 19:56:43
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
21页 1151K
描述
Bus Driver, AC Series, 2-Func, 4-Bit, Inverted Output, CMOS, PDSO20, GREEN, PLASTIC, SOIC-20

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SN74AC240DWE4 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.57系列：AC
JESD-30 代码：R-PDSO-G20长度：12.8 mm
逻辑集成电路类型：BUS DRIVER位数：4
功能数量：2端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：9 ns
座面最大高度：2.65 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

SN74AC240DWE4 数据手册

 浏览型号SN74AC240DWE4的Datasheet PDF文件第2页浏览型号SN74AC240DWE4的Datasheet PDF文件第3页浏览型号SN74AC240DWE4的Datasheet PDF文件第4页浏览型号SN74AC240DWE4的Datasheet PDF文件第5页浏览型号SN74AC240DWE4的Datasheet PDF文件第6页浏览型号SN74AC240DWE4的Datasheet PDF文件第7页 
SN54AC240, SN74AC240  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCAS512E − JUNE 1995 − REVISED OCTOBER 2003  
SN54AC240 . . . J OR W PACKAGE  
SN74AC240 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
2-V to 6-V V Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 6.5 ns at 5 V  
pd  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
VCC  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
description/ordering information  
These octal buffers and line drivers are designed  
specifically to improve the performance and  
density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters.  
The ’AC240 devices are organized as two 4-bit  
buffers/drivers with separate output-enable (OE)  
inputs. When OE is low, the device passes  
inverted data from the A inputs to the Y outputs.  
When OE is high, the outputs are in the  
high-impedance state.  
SN54AC240 . . . FK PACKAGE  
(TOP VIEW)  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
3
2
1
20 19  
18  
4
5
6
7
8
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
17  
16  
15  
14  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
PDIP − N  
Tube  
SN74AC240N  
SN74AC240N  
Tube  
SN74AC240DW  
SN74AC240DWR  
SN74AC240NSR  
SN74AC240DBR  
SN74AC240PW  
SN74AC240PWR  
SNJ54AC240J  
SOIC − DW  
AC240  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC240  
AC240  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
AC240  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC240J  
SNJ54AC240W  
SNJ54AC240FK  
Tube  
SNJ54AC240W  
SNJ54AC240FK  
−55°C to 125°C  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright © 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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