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SN65MLVD3DRBT PDF预览

SN65MLVD3DRBT

更新时间: 2024-11-24 04:31:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
17页 341K
描述
SINGLE M-LVDS RECEIVERS

SN65MLVD3DRBT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SON
包装说明:HVSON, SOLCC8,.12,25针数:8
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01风险等级:1.35
差分输出:NO驱动器位数:1
高电平输入电流最大值:0.00001 A输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-899; TIA-899
JESD-30 代码:S-PDSO-N8JESD-609代码:e4
长度:3 mm湿度敏感等级:2
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
最小输出摆幅:0.48 V输出特性:TOTEM-POLE
最大输出低电流:0.008 A输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVSON
封装等效代码:SOLCC8,.12,25封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
最大接收延迟:6 ns接收器位数:1
座面最大高度:1 mm子类别:Line Driver or Receivers
最大压摆率:25 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
电源电压1-最大:3.6 V电源电压1-分钟:3 V
电源电压1-Nom:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

SN65MLVD3DRBT 数据手册

 浏览型号SN65MLVD3DRBT的Datasheet PDF文件第2页浏览型号SN65MLVD3DRBT的Datasheet PDF文件第3页浏览型号SN65MLVD3DRBT的Datasheet PDF文件第4页浏览型号SN65MLVD3DRBT的Datasheet PDF文件第5页浏览型号SN65MLVD3DRBT的Datasheet PDF文件第6页浏览型号SN65MLVD3DRBT的Datasheet PDF文件第7页 
SN65MLVD2  
SN65MLVD3  
www.ti.com  
SLLS767NOVEMBER 2006  
SINGLE M-LVDS RECEIVERS  
FEATURES  
APPLICATIONS  
Parallel Multipoint Data and Clock  
Transmission via Backplanes and Cables  
Low-Voltage Differential 30-to 55-Line  
Receivers for Signaling Rates(1) up to  
250Mbps; Clock Frequencies up to 125MHz  
Cellular Base Stations  
Central Office Switches  
Network Switches and Routers  
SN65MLVD2 Type-1 Receiver Incorporates 25  
mV of Input Threshold Hysteresis  
SN65MLVD3 Type-2 Receiver Provides 100  
mV Offset Threshold to Detect Open-Circuit  
and Idle-Bus Conditions  
PACKAGE AND PIN-OUT  
SN65MLVD2DRB  
SN65MLVD3DRB  
SON-8  
Wide Receiver Input Common-Mode Voltage  
Range, –1 V to 3.4 V, Allows 2 V of Ground  
Noise  
VCC  
B
VCC  
1
2
3
4
8
Improved VIT (35 mV)  
RE  
R
7
Meets or Exceeds the M-LVDS Standard  
TIA/EIA-899 for Multipoint Topology  
A
6
5
High Input Impedance with Low Supply  
Voltage  
GND  
GND  
Bus-Pin HBM ESD Protection Exceeds 9 kV  
Packaged in 8-Pin SON (DRB) 70% Smaller  
Than 8-Pin SOIC  
(1)  
The signaling rate of a line is the number of voltage  
transitions that are made per second, expressed in the units  
bps (bits per second).  
DESCRIPTION  
The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full  
compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to  
250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding  
channel is enabled; when RE = high, the corresponding channel is disabled.  
The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers  
(SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with  
loss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver  
outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.  
The devices are characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN65MLVD3DRBT 替代型号

型号 品牌 替代类型 描述 数据表
SN65MLVD3DRBR TI

完全替代

SINGLE M-LVDS RECEIVERS
SN65MLVD3DRBTG4 TI

完全替代

SINGLE M-LVDS RECEIVERS
SN65MLVD3DRBRG4 TI

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SINGLE M-LVDS RECEIVERS

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