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SN65LVDM22IDR PDF预览

SN65LVDM22IDR

更新时间： 2024-09-24 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 中继器
页数 文件大小 规格书
14页 205K
描述
SPECIALTY INTERFACE CIRCUIT, PDSO16, SOIC-16

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中文翻译

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SN65LVDM22IDR 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknown风险等级：5.64
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：R-PDSO-G16
长度：9.9 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：1.75 mm标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：3.9 mm
Base Number Matches：1

SN65LVDM22IDR 数据手册

 浏览型号SN65LVDM22IDR的Datasheet PDF文件第2页浏览型号SN65LVDM22IDR的Datasheet PDF文件第3页浏览型号SN65LVDM22IDR的Datasheet PDF文件第4页浏览型号SN65LVDM22IDR的Datasheet PDF文件第5页浏览型号SN65LVDM22IDR的Datasheet PDF文件第6页浏览型号SN65LVDM22IDR的Datasheet PDF文件第7页 
SN65LVDS22  
SN65LVDM22  
www.ti.com  
SLLS315C–DECEMBER 1998–REVISED JUNE 2002  
DUAL MULTIPLEXED LVDS REPEATERS  
FEATURES  
SN65LVDS22D and SN65LVDS22PW (Marked as LVDS22)  
SN65LVDM22D and SN65LVDM22PW (Marked as LVDM22)  
(TOP VIEW)  
•
Meets or Exceeds the Requirements of ANSI  
TIA/EIA-644-1995 Standard  
1B  
1A  
S0  
VCC  
VCC  
1Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
•
Designed for Clock Rates up to 200 MHz  
(400 Mbps)  
•
•
Designed for Data Rates up to 250 Mbps  
1DE  
S1  
1Z  
2DE  
2Z  
Pin Compatible With SN65LVDS122 and  
SN65LVDT122, 1.5 Gbps 2x2 Crosspoint  
Switch From TI  
2A  
2B  
GND  
10 2Y  
GND  
9
•
•
•
ESD Protection Exceeds 12 kV on Bus Pins  
Operates From a Single 3.3-V Supply  
Low-Voltage Differential Signaling With  
Output Voltages of 350 mV Into:  
logic diagram (positive logic)  
– 100-Ω Load (SN65LVDS22)  
2
+
_
1A  
1B  
– 50-Ω Load (SN65LVDM22)  
14  
13  
0
1
1
1Y  
1Z  
•
•
•
Propagation Delay Time; 4 ns Typ  
Power Dissipation at 400 Mbps of 150 mW  
4
Bus Pins Are High Impedance When Disabled  
or With VCC Less Than 1.5 V  
1DE  
2DE  
S0  
12  
3
•
•
LVTTL Levels Are 5 V Tolerant  
Open-Circuit Fail Safe Receiver  
5
S1  
DESCRIPTION  
10  
11  
0
1
The SN65LVDS22 and SN65LVDM22 are differential  
line drivers and receivers that use low-voltage  
differential signaling (LVDS) to achieve signaling  
rates as high as 400 Mbps. The receiver outputs can  
be switched to either or both drivers through the  
multiplexer control signals S0 and S1. This allows the  
flexibility to perform splitter or signal routing functions  
with a single device.  
2Y  
2Z  
6
7
+
_
2A  
2B  
MUX TRUTH TABLE  
OUTPUT  
INPUT  
FUNCTION  
S1  
S0  
1Y/1Z  
1A/1B  
2A/2B  
1A/1B  
2A/2B  
2Y/2Z  
1A/1B  
2A/2B  
2A/2B  
1A/1B  
The TIA/EIA-644 standard compliant electrical  
interface provides a minimum differential output  
voltage magnitude of 247 mV into a 100-Ω load and  
receipt of 100 mV signals with up to 1 V of ground  
Splitter  
Splitter  
Router  
Router  
0
0
1
1
0
1
0
1
potential difference between  
a
transmitter and  
receiver. The SN65LVDM22 doubles the output drive  
current to achieve LVDS levels with a 50-Ω load.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1998–2002, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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