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SN65C1154 PDF预览

SN65C1154

更新时间: 2024-11-19 22:42:55
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德州仪器 - TI 驱动器
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12页 360K
描述
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS

SN65C1154 数据手册

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SN65C1154, SN75C1154  
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS  
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003  
SN65C1154 . . . N PACKAGE  
SN75C1154 . . . DW, N, OR NS PACKAGE  
(TOP VIEW)  
Meet or Exceed the Requirements of  
TIA/EIA-232-F and ITU Recommendation  
V.28  
Very Low Power Consumption . . .  
5 mW Typ  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
V
CC  
DD  
1RA  
1DY  
2RA  
2DY  
3RA  
3DY  
4RA  
4DY  
1RY  
1DA  
2RY  
2DA  
3RY  
3DA  
4RY  
4DA  
GND  
Wide Driver Supply Voltage . . .  
±4.5 V to ±15 V  
Driver Output Slew Rate Limited to  
30 V/µs Max  
Receiver Input Hysteresis . . . 1000 mV Typ  
Push-Pull Receiver Outputs  
On-Chip Receiver 1-µs Noise Filter  
V
SS  
description/ordering information  
The SN65C1164 and SN75C1154 are low-power BiMOS devices containing four independent drivers and  
receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment  
(DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1154  
and SN75C1154 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver,  
respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs and the  
receivers have filters that reject input noise pulses of shorter than 1 µs. Both these features eliminate the need  
for external components.  
The SN65C1154 and SN75C1154 have been designed using low-power techniques in a BiMOS technology.  
In most applications, the receivers contained in these devices interface to single inputs of peripheral devices  
such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices usually are insensitive  
to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the  
SN65C1154 and SN75C1154 receiver outputs be buffered by single Schmitt input gates or single gates of the  
HCMOS, ALS, or 74F logic families.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
–40°C to 85°C  
PDIP (N)  
PDIP (N)  
Tube of 20  
Tube of 20  
Tube of 25  
Reel of 2500  
Reel of 2000  
SN65C1154N  
SN65C1154N  
SN75C1154N  
SN75C1154N  
SN75C1154DW  
SN75C1154DWR  
SN75C1154NSR  
0°C to 70°C  
SOIC (DW)  
SOP (NS)  
SN75C1154  
SN75C1154  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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