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SN64BCT657NT

更新时间： 2024-11-14 19:55:03
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
7页 111K
描述
Octal Transceiver With Parity Generator/Checker And 3-State Outputs 24-PDIP -40 to 85

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SN64BCT657NT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.92控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：BCT/FBT
JESD-30 代码：R-PDIP-T24长度：31.64 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
传播延迟（tpd）：9.3 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：BICMOS温度等级：INDUSTRIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.62 mm
Base Number Matches：1

SN64BCT657NT 数据手册

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SN64BCT657  
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER  
AND 3-STATE OUTPUTS  
SCBS090A – NOVEMBER 1991 – REVISED JANUARY 1994  
DW OR NT PACKAGE  
• State-of-the-Art BiCMOS Design  
Significantly Reduces I  
(TOP VIEW)  
CCZ  
• ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
T/R  
A1  
A2  
A3  
A4  
A5  
OE  
1
24  
2
23 B1  
22 B2  
3
• High-Impedance State During Power Up  
4
21  
20  
19  
18  
17  
16  
15  
14  
13  
B3  
B4  
GND  
GND  
B5  
B6  
B7  
B8  
PARITY  
and Power Down  
5
6
• 3-State B Outputs Sink 64 mA and Source  
7
V
15 mA  
CC  
A6  
8
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic 300-mil DIPs (NT)  
9
A7  
A8  
10  
11  
12  
ODD/EVEN  
ERR  
description  
The SN64BCT657 contains eight noninverting buffers with parity generator/checker circuits and control signals.  
The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the  
A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode).  
When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state.  
Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity  
bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity  
generator/checker in the receive mode.  
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic  
level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN  
is low (even parity selected) and there are five high bits on the A bus, then PARITY is set to the logic high level  
so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.  
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic  
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if  
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, then ERR  
is low, indicating a parity error.  
The SN64BCT657 is characterized for operation from –40°C to 85°C and 0°C to 70°C.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
3–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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