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SN54LVTH652W

更新时间： 2024-11-23 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
10页 154K
描述
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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SN54LVTH652W 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：24
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：LVT
JESD-30 代码：R-GDFP-F24长度：14.36 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
最大电源电流（ICC）：5 mA传播延迟（tpd）：5.9 ns
认证状态：Not Qualified座面最大高度：2.29 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：9.09 mm
Base Number Matches：1

SN54LVTH652W 数据手册

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SN54LVTH652, SN74LVTH652  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS706D – AUGUST 1997 – REVISED APRIL 1999  
SN54LVTH652 . . . JT OR W PACKAGE  
SN74LVTH652 . . . DB, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLKAB  
SAB  
OEAB  
A1  
V
CC  
I
and Power-Up 3-State Support Hot  
2
off  
CLKBA  
SBA  
OEBA  
B1  
Insertion  
3
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
4
5
A2  
6
A3  
B2  
7
A4  
B3  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
8
A5  
B4  
9
A6  
B5  
3.3-V V  
)
CC  
10  
11  
12  
A7  
A8  
GND  
B6  
B7  
B8  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
SN54LVTH652 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
4
3
2
1
28 27 26  
25  
Package Options Include Plastic  
5
6
7
8
9
A1  
A2  
A3  
NC  
A4  
A5  
A6  
OEBA  
B1  
B2  
NC  
B3  
B4  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Thin Very Small-Outline (DGV) Packages,  
Ceramic Chip Carriers (FK), Ceramic Flat  
(W) Package, and Ceramic (JT) DIPs  
24  
23  
22  
21  
20  
19  
10  
11  
B5  
description  
12 13 14 15 16 17 18  
These bus transceivers and registers are  
designed specifically for low-voltage (3.3-V) V  
CC  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
NC – No internal connection  
The ’LVTH652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the data bus or from the internal storage registers.  
Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB  
and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for  
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between  
real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1  
illustrates the four fundamental bus-management functions that can be performed with the ’LVTH652 devices.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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