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SN54LS375 PDF预览

SN54LS375

更新时间: 2024-09-26 23:03:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
5页 167K
描述
4-BIT D LATCH

SN54LS375 数据手册

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SN54/74LS375  
4-BIT D LATCH  
The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage  
for binary information between processing limits and input/output or indicator  
units. When the Enable (E) is HIGH, information present at the D input will be  
transferred to the Q output and, if E is HIGH, the Q output will follow the input.  
WhenEgoesLOW, theinformationpresentattheDinputpriortoitssetuptime  
will be retained at the Q outputs.  
4-BIT D LATCH  
LOW POWER SCHOTTKY  
CONNECTION DIAGRAM DIP (TOP VIEW)  
NOTE:  
J SUFFIX  
CERAMIC  
CASE 620-09  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
16  
1
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
TRUTH TABLE  
NOTES:  
(Each latch)  
t
= bit time before enable  
n
t
t
n+1  
D SUFFIX  
SOIC  
CASE 751B-03  
n
negative-going transition.  
= bit time after enable  
t
n+1  
negative-going transition.  
D
H
L
Q
H
L
16  
1
PIN NAMES  
LOADING (Note a)  
ORDERING INFORMATION  
HIGH  
LOW  
SN54LSXXXJ  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
Ceramic  
D D  
0.5 U.L.  
2.0 U.L.  
2.0 U.L.  
10 U.L.  
10 U.L.  
0.25 U.L.  
1.0 U.L.  
1.0 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
Data Inputs  
1
4
E
0–1  
E
2–3  
Enable Input Latches 0, 1  
Enable Input Latches 2, 3  
Latch Outputs (Note b)  
Complimentary Latch Outputs (Note b)  
Q Q  
1
4
4
Q Q  
1
NOTES:  
LOGIC SYMBOL  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74)  
Temperature Ranges.  
LOGIC DIAGRAM  
FAST AND LS TTL DATA  
5-528  

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