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SN54LS05W-10 PDF预览

SN54LS05W-10

更新时间: 2024-11-04 15:51:59
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
22页 904K
描述
LS SERIES, HEX 1-INPUT INVERT GATE, CDFP14

SN54LS05W-10 技术参数

生命周期:Obsolete包装说明:DFP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.51系列:LS
JESD-30 代码:R-GDFP-F14长度:9.21 mm
负载电容(CL):15 pF逻辑集成电路类型:INVERTER
功能数量:6输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-COLLECTOR
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
最大电源电流(ICC):6.6 mA传播延迟(tpd):28 ns
认证状态:Not Qualified座面最大高度:2.03 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL宽度:6.29 mm
Base Number Matches:1

SN54LS05W-10 数据手册

 浏览型号SN54LS05W-10的Datasheet PDF文件第2页浏览型号SN54LS05W-10的Datasheet PDF文件第3页浏览型号SN54LS05W-10的Datasheet PDF文件第4页浏览型号SN54LS05W-10的Datasheet PDF文件第5页浏览型号SN54LS05W-10的Datasheet PDF文件第6页浏览型号SN54LS05W-10的Datasheet PDF文件第7页 
ꢀꢁ ꢇꢃ ꢅ ꢂ ꢆ ꢀꢁꢇ ꢃ ꢄ ꢀꢅ ꢂ ꢆ ꢀ ꢁꢇ ꢃꢀ ꢅ  
The SN5405 is obsolete  
and no longer is supplied.  
SDLS030A − DECEMBER 1983 − REVISED NOVEMBER 2003  
D
Package Options Include Plastic  
D
Dependable Texas Instrument Quality and  
Reliability  
Small-Outline (D, NS), Shrink Small-Outline  
(DB), and Ceramic Flat (W) Packages,  
Ceramic Chip Carriers (FK), and Standard  
Plastic (N) and Ceramic (J) DIPs  
SN54LS05, SN54S05 . . . FK PACKAGE  
(TOP VIEW)  
SN5405, SN54LS05, SN54S05 . . . J PACKAGE  
SN7405 . . . N PACKAGE  
SN74LS05 . . . D, DB, N, OR NS PACKAGE  
SN74S05 . . . D, N, OR NS PACKAGE  
(TOP VIEW)  
SN54LS05, SN54S05 . . . W PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
6Y  
NC  
5A  
NC  
5Y  
2A  
NC  
2Y  
4
5
6
7
8
17  
16  
15  
14  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1A  
2Y  
2A  
1Y  
6A  
6Y  
GND  
5Y  
1A  
1Y  
2A  
2Y  
3A  
V
CC  
6A  
6Y  
5A  
5Y  
4A  
4Y  
NC  
3A  
V
CC  
3A  
9 10 11 12 13  
3Y  
4A  
5A  
4Y  
3Y  
GND  
8
8
NC − No internal connection  
description/ordering information  
These devices contain six independent inverters. To perform correctly, the open-collector outputs require pullup  
resistors. These devices may be connected to other open-collector outputs to implement active-low wired-OR  
or active-high wire-AND functions. Open-collector devices often are used to generate high V  
levels.  
OH  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SN7405N  
SN7405N  
SN74LS05N  
SN74S05N  
SN74LS05N  
SN74S05N  
PDIP − N  
SOIC − D  
Tube  
Tube  
SN74LS05D  
SN74LS05DR  
SN74S05D  
LS05  
S05  
Tape and reel  
Tube  
0°C to 70°C  
Tape and reel  
SN74S05DR  
SN74LS05NSR  
SN74S05NSR  
SN74LS05DBR  
SNJ54LS05J  
SNJ54S05J  
74LS05  
SOP − NS  
Tape and reel  
Tape and reel  
74S05  
SSOP − DB  
LS05  
SNJ54LS05J  
SNJ54S05J  
SNJ54LS05W  
SNJ54S05W  
SNJ54LS05FK  
CDIP − J  
Tube  
Tube  
Tube  
SNJ54LS05W  
SNJ54S05W  
SNJ54LS05FK  
−55°C to 125°C  
CDIP − W  
LCCC − FK  
SNJ54S05FK  
SNJ54S05FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢐ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢋ ꢄꢒ ꢑꢍ ꢮ ꢒꢯꢰꢂ ꢯꢂꢆ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢐ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢆ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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