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SN54AS74A

更新时间: 2024-11-14 22:39:15
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德州仪器 - TI 触发器
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描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN54AS74A 数据手册

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SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SDAS143C – APRIL 1982 – REVISED AUGUST 1995  
SN54ALS74A, SN54AS74A . . . J PACKAGE  
SN74ALS74A, SN74AS74A . . . D OR N PACKAGE  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
(TOP VIEW)  
1CLR  
1D  
1CLK  
1PRE  
1Q  
V
CC  
2CLR  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
TYPICAL MAXIMUM  
CLOCK FREQUENCY  
TYPICAL POWER  
DISSIPATION  
PER FLIP-FLOP  
(mW)  
2D  
TYPE  
2CLK  
2PRE  
2Q  
(C = 50 pF)  
L
(MHz)  
50  
ALS74A  
AS74A  
6
1Q  
GND  
2Q  
8
134  
26  
description  
SN54ALS74A, SN54AS74A . . . FK PACKAGE  
(TOP VIEW)  
These devices contain two independent  
positive-edge-triggered D-type flip-flops. A low  
level at the preset (PRE) or clear (CLR) inputs sets  
or resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the data (D) input meeting the  
setup-time requirements are transferred to the  
outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a voltage  
level and is not directly related to the rise time of  
CLK. Following the hold-time interval, data at the  
D input can be changed without affecting the  
levels at the outputs.  
3
2
1
20 19  
18  
1CLK  
NC  
2D  
17 NC  
4
5
6
7
8
16  
15  
14  
1PRE  
NC  
2CLK  
NC  
1Q  
2PRE  
9 10 11 12 13  
NC – No internal connection  
The SN54ALS74A and SN54AS74A are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS74AandSN74AS74Aarecharacterized  
for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
The output levels in this configuration are not  
specifiedtomeettheminimumlevelsforV ifthe  
OH  
lows at PRE and CLR are near V maximum.  
IL  
Furthermore, this configuration is nonstable; that  
is, it does not persist when PRE or CLR returns to  
its inactive (high) level.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN54AS74A 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS74A TI

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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