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SN54AS160J PDF预览

SN54AS160J

更新时间： 2024-11-27 20:05:27
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 158K
描述
AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, 0.300 INCH, CERAMIC, DIP-16

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SN54AS160J 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.81
其他特性：TCO OUTPUT计数方向：UP
系列：ASJESD-30 代码：R-GDIP-T16
长度：19.56 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：DECADE COUNTER
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
最大电源电流（ICC）：53 mA传播延迟（tpd）：14 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Counters最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：65 MHz
Base Number Matches：1

SN54AS160J 数据手册

 浏览型号SN54AS160J的Datasheet PDF文件第2页浏览型号SN54AS160J的Datasheet PDF文件第3页浏览型号SN54AS160J的Datasheet PDF文件第4页浏览型号SN54AS160J的Datasheet PDF文件第5页浏览型号SN54AS160J的Datasheet PDF文件第6页浏览型号SN54AS160J的Datasheet PDF文件第7页 
SN54ALS160B THRU SN54ALS163B, SN54AS160 THRU SN54AS163  
SN74ALS160B THRU SN74ALS163B, SN74AS160 THRU SN74AS163  
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS  
SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986  
SN54ALS’, SN54AS’ . . . J PACKAGE  
SN74ALS’, SN74AS’ . . . D OR N PACKAGE  
• Internal Look-Ahead for Fast Counting  
• Carry Output for n-Bit Cascading  
• Synchronous Counting  
(TOP VIEW)  
• Synchronously Programmable  
V
RCO  
Q
Q
B
Q
Q
D
ENT  
LOAD  
CLR  
CLK  
A
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
• Package Options include Plastic Small  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
A
B
C
D
C
• Dependable Texas Instruments Quality and  
ENP  
GND  
Reliability  
description  
SN54ALS’, SN54AS’ . . . FK PACKAGE  
(TOP VIEW)  
These synchronous, presettable counters feature  
an internal carry look-ahead for application in  
high-speed counting designs. The ’ALS160B,  
’ALS162B, ’AS160, and ’AS162 are decade  
counters, and the ’ALS161B, ’ALS163B, ’AS161,  
and ’AS163 are 4-bit binary counters. Synchro-  
nous operation is provided by having all flip-flops  
clocked simultaneously so that the outputs  
change coincident with each other when so  
instructed by the count-enable inputs and internal  
gating. This mode of operation eliminates the  
output counting spikes that are normally asso-  
ciated with asynchronous (ripple clock)  
counters. A buffered clock input triggers the four  
flip-flops on the rising (positive-going) edge of the  
clock input waveform.  
3
2
1
20 19  
18  
Q
Q
A
B
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
NC  
C
Q
C
Q
D
D
9 10 11 12 13  
NC–No internal connection  
These counters are fully programmable; that is, they may be preset to any number between 0 and 9, or 15. As  
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs  
to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.  
Theclearfunctionforthe’ALS160B, ’ALS161B, ’AS160, and’AS161isasynchronousandalowlevelattheclear  
input sets all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs. This  
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum  
count desired. The active-low output of the gate used for decoding is connected to the clear input to  
synchronously clear the counter to 0000 (LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry  
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the  
ripple carry output. The ripple carry output (RCO) thus enabled will produce a high-level pulse while the count  
is maximum (9 or 15 with Q high). This high-level overflow ripple carry pulse can be used to enable successive  
A
cascaded stages. Transitions at the ENP or ENT are allowed regardless of the level of the clock input.  
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function  
of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting  
the stable setup and hold times.  
The SN54ALS160B through SN54ALS163B and SN54AS160 through SN54AS163 are characterized for  
operation over the full military temperature range of –55°C to 125°C. The SN74ALS160B through  
SN74ALS163B and SN74AS160 through SN74AS163 are characterized for operation from 0°C to 70°C.  
Copyright 1986, Texas Instruments Incorporated  
5BASIC  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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