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SN54ALVTH16501WD

更新时间： 2024-09-30 09:18:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
11页 172K
描述
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54ALVTH16501WD 数据手册

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SN54ALVTH16501, SN74ALVTH16501  
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCES071D – JUNE 1996 – REVISED JANUARY 1999  
SN54ALVTH16501 . . . WD PACKAGE  
SN74ALVTH16501 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
OEAB  
LEAB  
A1  
GND  
A2  
GND  
CLKAB  
B1  
GND  
B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Widebus Design for  
2.5-V and 3.3-V Operation and Low Static  
Power Dissipation  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 2.3-V to  
A3  
B3  
V
V
CC  
CC  
3.6-V V  
)
CC  
A4  
A5  
B4  
B5  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A6 10  
47 B6  
A
GND  
A7  
GND  
B7  
11  
12  
46  
45  
High Drive (–24/24 mA at 2.5-V and  
–32/64 mA at 3.3-V V  
)
CC  
A8 13  
A9 14  
44 B8  
Power Off Disables Outputs, Permitting  
Live Insertion  
43 B9  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
High-Impedance State During Power Up  
and Power Down Prevents Driver Conflict  
Use Bus Hold on Data Inputs in Place of  
External Pullup/Pulldown Resistors to  
Prevent the Bus From Floating  
Auto3-State Eliminates Bus Current  
Loading When Output Exceeds V  
+ 0.5 V  
V
22  
35  
V
CC  
CC  
CC  
A16 23  
34 B16  
Flow-Through Architecture Facilitates  
Printed Circuit Board Layout  
A17 24  
33 B17  
GND 25  
A18 26  
32 GND  
31 B18  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
OEBA 27  
LEBA 28  
30 CLKBA  
29 GND  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), Thin Very  
Small-Outline (DGV) Packages, and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
description  
The ’ALVTH16501 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V operation, but  
CC  
with the capability to provide a TTL interface to a 5-V system environment.  
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),  
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when  
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is  
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the  
B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state.  
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are  
complementary (OEAB is active high and OEBA is active low).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
UBT and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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