SN54ALVTH32373, SN74ALVTH32373
2.5-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES322A – FEBRUARY 2000 – REVISED APRIL 2000
State-of-the-Art Advanced BiCMOS
Auto3-State Eliminates Bus Current
Technology (ABT) Widebus+ Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
Loading When Output Exceeds V
+ 0.5 V
CC
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
3.6-V V
)
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
)
CC
I
and Power-Up 3-State Support Hot
– 1000-V Charged-Device Model (C101)
off
Insertion
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
NOTE: For tape and reel order entry:
The GKER package is abbreviated to KR.
description
The’ALVTH32373devicesare32-bittransparentD-typelatcheswith3-stateoutputsdesignedfor2.5-Vor3.3-V
operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices
V
CC
are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
These devices can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable
(LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at
the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
When V is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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