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SN54ALS74AFK PDF预览

SN54ALS74AFK

更新时间: 2024-09-26 22:36:59
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
7页 116K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN54ALS74AFK 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFN包装说明:CERAMIC, CC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.48
Is Samacsys:N系列:ALS
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:30000000 Hz最大I(ol):0.004 A
位数:1功能数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):4 mA
传播延迟(tpd):20 ns认证状态:Not Qualified
座面最大高度:2.03 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.89 mm
最小 fmax:25 MHzBase Number Matches:1

SN54ALS74AFK 数据手册

 浏览型号SN54ALS74AFK的Datasheet PDF文件第2页浏览型号SN54ALS74AFK的Datasheet PDF文件第3页浏览型号SN54ALS74AFK的Datasheet PDF文件第4页浏览型号SN54ALS74AFK的Datasheet PDF文件第5页浏览型号SN54ALS74AFK的Datasheet PDF文件第6页浏览型号SN54ALS74AFK的Datasheet PDF文件第7页 
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SDAS143C – APRIL 1982 – REVISED AUGUST 1995  
SN54ALS74A, SN54AS74A . . . J PACKAGE  
SN74ALS74A, SN74AS74A . . . D OR N PACKAGE  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
(TOP VIEW)  
1CLR  
1D  
1CLK  
1PRE  
1Q  
V
CC  
2CLR  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
TYPICAL MAXIMUM  
CLOCK FREQUENCY  
TYPICAL POWER  
DISSIPATION  
PER FLIP-FLOP  
(mW)  
2D  
TYPE  
2CLK  
2PRE  
2Q  
(C = 50 pF)  
L
(MHz)  
50  
ALS74A  
AS74A  
6
1Q  
GND  
2Q  
8
134  
26  
description  
SN54ALS74A, SN54AS74A . . . FK PACKAGE  
(TOP VIEW)  
These devices contain two independent  
positive-edge-triggered D-type flip-flops. A low  
level at the preset (PRE) or clear (CLR) inputs sets  
or resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the data (D) input meeting the  
setup-time requirements are transferred to the  
outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a voltage  
level and is not directly related to the rise time of  
CLK. Following the hold-time interval, data at the  
D input can be changed without affecting the  
levels at the outputs.  
3
2
1
20 19  
18  
1CLK  
NC  
2D  
17 NC  
4
5
6
7
8
16  
15  
14  
1PRE  
NC  
2CLK  
NC  
1Q  
2PRE  
9 10 11 12 13  
NC – No internal connection  
The SN54ALS74A and SN54AS74A are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS74AandSN74AS74Aarecharacterized  
for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
The output levels in this configuration are not  
specifiedtomeettheminimumlevelsforV ifthe  
OH  
lows at PRE and CLR are near V maximum.  
IL  
Furthermore, this configuration is nonstable; that  
is, it does not persist when PRE or CLR returns to  
its inactive (high) level.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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