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SN54ALS161BFKR PDF预览

SN54ALS161BFKR

更新时间: 2024-11-23 13:01:43
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德州仪器 - TI 计数器
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SN54ALS161BFKR 数据手册

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SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163  
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163  
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS  
SDAS276 – DECEMBER 1994  
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,  
Internal Look-Ahead Circuitry for Fast  
SN54AS163 . . . J PACKAGE  
SN74ALS161B, SN74ALS163B, SN74AS161,  
SN74AS163 . . . D OR N PACKAGE  
(TOP VIEW)  
Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
Synchronously Programmable  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q
A
B
C
D
Q
B
Q
C
Q
D
ENT  
description  
ENP  
GND  
LOAD  
These synchronous, presettable, 4-bit decade  
and binary counters feature an internal carry  
look-ahead circuitry for application in high-speed  
counting designs. The SN54ALS162B is a 4-bit  
decade counter. The ALS161B, ALS163B,  
AS161, and AS163 are 4-bit binary counters.  
Synchronous operation is provided by having all  
flip-flops clocked simultaneously so that the  
outputs change coincidentally with each other  
when instructed by the count-enable (ENP, ENT)  
inputs and internal gating. This mode of operation  
eliminates the output counting spikes normally  
associated with asynchronous (ripple-clock)  
counters. A buffered clock (CLK) input triggers the  
four flip-flops on the rising (positive-going) edge of  
the clock input waveform.  
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,  
SN54AS163 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
Q
C
D
Q
D
9 10 11 12 13  
These counters are fully programmable; they may  
be preset to any number between 0 and 9 or 15.  
Because presetting is synchronous, setting up a  
low level at the load (LOAD) input disables the  
counter and causes the outputs to agree with the  
setup data after the next clock pulse, regardless of  
the levels of the enable inputs.  
NC – No internal connection  
The clear function for the ALS161B and AS161 is asynchronous. A low level at the clear (CLR) input sets all  
four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function  
for the SN54ALS162B, ALS163B, and AS163 is synchronous, and a low level at CLR sets all four of the flip-flop  
outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear  
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The  
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to  
0000 (LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this  
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,  
produces a high-level pulse while the count is maximum (9 or 15 with Q high). The high-level overflow  
A
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,  
regardless of the level of CLK.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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