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SN54ALS114A

更新时间： 2024-11-20 12:22:47
品牌 Logo 应用领域
德州仪器 - TI 触发器时钟
页数 文件大小 规格书
4页 75K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR AND COMMON CLOCK

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SN54ALS114A 数据手册

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SDAS201 − D2661, DECEMBER 1982 − REVISED MAY 1986  
• Fully Buffered to Offer Maximum isolation  
SN54ALS114A . . . J PACKAGE  
SN74ALS114A . . . D OR N PACKAGE  
from External Disturbance  
(TOP VIEW)  
• Package Options include Plastic Small  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
V
CLK  
2K  
2J  
2PRE  
2Q  
2Q  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CLR  
1K  
1J  
1PRE  
1Q  
CC  
• Typical Maximum Clock Frequency  
30 MHz  
• Typical Power Dissipation per Flip-Flop  
1Q  
GND  
6 mW  
8
• Dependable Texas Instruments Quality and  
Reliability  
SN54ALS114A . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain two independent J-K  
negative-edge-triggered flip-flops. A low level at  
the Preset or Clear inputs sets or resets the  
outputs regardless of the levels of the other inputs.  
When Preset and Clear are inactive (high), data at  
the J and K inputs meeting the setup time  
requirements are transferred to the outputs on the  
negative-going edge of the clock pulse. Clock  
triggering occurs at a voltage level and is not  
directly related to the fall time of the clock pulse.  
Following the hold time interval, data at the J and  
K inputs may be changed without affecting the  
levels at the outputs. These versatile flip-flops can  
perform as toggle flip-flops by tying J and K high.  
3
2
1
20 19  
18  
2K  
1J  
NC  
4
5
6
7
8
NC  
2J  
17  
16  
15  
14  
1PRE  
NC  
NC  
2PRE  
1Q  
9 10 11 12 13  
NC−No internal connection  
‡
logic symbol  
The SN54ALS114A is characterized for operation  
over the full military temperature range of −55°C  
to 125°C. The SN74ALS114A is characterized for  
operation from 0°C to 70°C.  
1
CLR  
R
S
13  
CLK  
C1  
FUNCTION TABLE  
4
1PRE  
INPUTS  
OUTPUTS  
5
6
3
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
1J  
1J  
1Q  
1Q  
2
1K  
1K  
H
L
X
H
10  
9
8
†
†
L
L
X
H
H
2PRE  
2Q  
2Q  
H
H
↓
Q
Q
0
0
11  
2J  
H
H
↓
H
L
L
H
L
12  
H
H
↓
H
H
X
L
H
2K  
H
H
↓
H
X
TOGGLE  
H
H
H
Q
Q
0
0
‡
This symbol is in accordance with ANSI/IEEE Std 911-1984 and  
IEC Publication 617-12.  
†
The output levels in this configuration are not guaranteed to  
meet the minimum levels for V if the lows at Preset and  
Clear are near V maximum. Furthermore, this configuration  
OH  
Pin numbers are for D, J, and N packages.  
IL  
is nonstable; that is, it will not persist when either Preset or  
Clear returns to its inactive (high) level.  
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Copyright 1986, Texas Instruments Incorporated  
5BASIC  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
1234

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