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SN54AHCT174W PDF预览

SN54AHCT174W

更新时间： 2024-11-24 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
6页 104K
描述
HEX D-TYPE FLIP-FLOPS WITH CLEAR

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SN54AHCT174W 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：AHCT/VHCT
JESD-30 代码：R-GDFP-F16长度：10.2 mm
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：6端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：10 ns
认证状态：Not Qualified座面最大高度：2.03 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：6.73 mm最小 fmax：80 MHz
Base Number Matches：1

SN54AHCT174W 数据手册

 浏览型号SN54AHCT174W的Datasheet PDF文件第2页浏览型号SN54AHCT174W的Datasheet PDF文件第3页浏览型号SN54AHCT174W的Datasheet PDF文件第4页浏览型号SN54AHCT174W的Datasheet PDF文件第5页浏览型号SN54AHCT174W的Datasheet PDF文件第6页 
SN54AHCT174, SN74AHCT174  
HEX D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS419E – JUNE 1998 – REVISED JANUARY 2000  
SN54AHCT174 . . . J OR W PACKAGE  
SN74AHCT174 . . . D, DB, DGV, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Inputs Are TTL-Voltage Compatible  
Contain Six Flip-Flops With Single-Rail  
Outputs  
CLR  
1Q  
1D  
2D  
2Q  
3D  
3Q  
GND  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
6Q  
6D  
5D  
5Q  
4D  
4Q  
CLK  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
– Pattern Generators  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
SN54AHCT174 . . . FK PACKAGE  
(TOP VIEW)  
– 1000-V Charged-Device Model (C101)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), Thin  
Shrink Small-Outline (PW), and Ceramic  
Flat (W) Packages, Ceramic Chip Carriers  
(FK), and Standard Plastic (N) and Ceramic  
(J) DIPs  
3
2
1 20 19  
18 6D  
1D  
2D  
NC  
2Q  
3D  
4
5
6
7
8
17  
5D  
NC  
5Q  
4D  
16  
15  
14  
9 10 11 12 13  
description  
These monolithic positive-edge-triggered D-type  
flip-flops have a direct clear (CLR) input.  
NC – No internal connection  
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the  
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not  
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low  
level, the D input has no effect at the output.  
The SN54AHCT174 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHCT174 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLR  
L
CLK  
D
X
H
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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