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SMBJ18 PDF预览

SMBJ18

更新时间: 2024-11-28 06:12:19
品牌 Logo 应用领域
SSC 二极管
页数 文件大小 规格书
4页 755K
描述
Transient Voltage Suppressors

SMBJ18 数据手册

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SMBJ Series  
Transient Voltage Suppressors  
PRODUCT SUMMARY  
Stand-off Voltage ratings from 5.0V to 440V  
Peak pulse power 600W in SMB surface-mount package  
FEATURES  
Plastic package has Underwriters Laboratory Flammability  
Classification 94V-0  
Low profile package with built-in strain relief for surface-mount  
Glass passivated junction  
Low incremental surge resistance, excellent clamping capability  
Peak pulse power capability of 600W with a 10/1000us waveform,  
repetition rate (duty cycle): 0.01%  
Very fast response time  
High temperature soldering guaranteed:  
260°C for 10 seconds at terminals  
MECHANICAL DATA  
Case: JEDEC DO-214AA (SMB) molded plastic over passivated chip  
Terminals: Matte-Sn plated, solderable per MIL-STD-750,  
Method 2026  
Polarity: For uni-directional types the band denotes the cathode, which  
is positive with respect to the anode under normal TVS operation.  
Mounting position: Any  
Weight: 0.003oz., 0.093g  
Pb-free; RoHS-compliant  
Devices for Bidirectional Applications  
For bi-directional devices, use suffix CA (e.g. SMBJ10CA). Electrical characteristics apply in both directions.  
MAXIMUM RATINGS  
Rating at 25°C ambient temperature unless otherwise specified.  
Parameter  
Symbol  
Value  
Unit  
Peak pulse power dissipation with  
PPPM  
IPPM  
Minimum 600  
See Next Table  
100  
W
A
a 10/1000us waveform (1,2) (see Fig. 1)  
Peak pulse current with a 10/1000us waveform (1)  
Peak forward surge current, 8.3ms single half sine-wave  
uni-directional only (2)  
IFSM  
A
Typical thermal resistance, junction to ambient (3)  
RθJA  
RθJL  
100  
20  
°C/W  
°C/W  
°C  
Typical thermal resistance, junction to lead  
Operating junction and storage temperature range  
TJ, TSTG  
-55 to +150  
Notes: 1. Non-repetitive current pulse, per Fig. 3 and derated above TA=25°C per Fig. 2.  
2. Mounted on 0.2" x 0.2" (5.0 mm x 5.0 mm) copper pads at each terminal  
3. Mounted on minimum recommended pad layout  
9/21/2006 Rev.4.01  
www.SiliconStandard.com  
1 of 4  

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